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| author | Matt Ettus <matt@ettus.com> | 2010-07-09 14:21:48 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-07-09 14:21:48 -0700 |
| commit | 42a98490a78ab08615dafe688848010c1a97ccfe (patch) | |
| tree | 5f161d37dd9d7b81cb00c3e50fafa0f8c28804d8 /usrp2/vrt/vita_rx.build | |
| parent | 7c50d20eb44f93e29669dc383f056e692f1654f3 (diff) | |
| download | uhd-42a98490a78ab08615dafe688848010c1a97ccfe.tar.gz uhd-42a98490a78ab08615dafe688848010c1a97ccfe.tar.bz2 uhd-42a98490a78ab08615dafe688848010c1a97ccfe.zip | |
updated tests to match new features
Diffstat (limited to 'usrp2/vrt/vita_rx.build')
| -rwxr-xr-x | usrp2/vrt/vita_rx.build | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/vrt/vita_rx.build b/usrp2/vrt/vita_rx.build index f6d2d75a3..010d1be6e 100755 --- a/usrp2/vrt/vita_rx.build +++ b/usrp2/vrt/vita_rx.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v +iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v |