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| author | Matt Ettus <matt@ettus.com> | 2010-05-27 17:31:46 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-27 17:31:46 -0700 |
| commit | 3d06fb26c5a59451b26680b6096fca7ee37e8018 (patch) | |
| tree | ce172a14304474b2a46854bea6b47c2ed1f8380b /usrp2/vrt/.gitignore | |
| parent | 621ad7cc9e68b4e304b616d8f840d3a03a047c8b (diff) | |
| parent | b38d2424b1ac3242146fc9305d9e4ae80e21dede (diff) | |
| download | uhd-3d06fb26c5a59451b26680b6096fca7ee37e8018.tar.gz uhd-3d06fb26c5a59451b26680b6096fca7ee37e8018.tar.bz2 uhd-3d06fb26c5a59451b26680b6096fca7ee37e8018.zip | |
Merge branch 'udp' into master_merge_take2
* udp: (67 commits)
better test program for just the tx side
fix typo, no functionality difference
ignores
move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing
reverting logic clean up which should have made timing better, but made it worse instead
moved fifos around, now easier to see where they are and how big
bigger fifo on UDP TX path, to possibly fix overruns on decim=4
Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround
pps and vita time debug pins
ignore emacs backup files
more debug for fixing E's
better debug pins for going after cascading E's
copy in wrong place
copied over from quad radio
just debug pin changes
typo caused the tx udp chain to be disconnected
moved into subdir
speed up timing by ignoring the too_early error. We'll need to FIXME this later
Added set time and set time at next pps. Removed the old sync pps commands, they dont make sense to use anymore.
moved around regs, added a bit to allow for alternate PPS source
...
Diffstat (limited to 'usrp2/vrt/.gitignore')
| -rw-r--r-- | usrp2/vrt/.gitignore | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/usrp2/vrt/.gitignore b/usrp2/vrt/.gitignore new file mode 100644 index 000000000..446b2daae --- /dev/null +++ b/usrp2/vrt/.gitignore @@ -0,0 +1,4 @@ +vita_rx_tb +vita_tx_tb +*.vcd +*.sav |