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| author | Matt Ettus <matt@ettus.com> | 2010-03-25 14:00:37 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-03-25 14:00:37 -0700 |
| commit | fdb6175aef0aa1896c6319d5425955ce0a5dc86b (patch) | |
| tree | c220d8bfe85325d45286a1919a6cb99a82c314e5 /usrp2/udp | |
| parent | dce164d82eac11e2fc74d91d4c144ef4fff0be49 (diff) | |
| download | uhd-fdb6175aef0aa1896c6319d5425955ce0a5dc86b.tar.gz uhd-fdb6175aef0aa1896c6319d5425955ce0a5dc86b.tar.bz2 uhd-fdb6175aef0aa1896c6319d5425955ce0a5dc86b.zip | |
moved fifos around, now easier to see where they are and how big
Diffstat (limited to 'usrp2/udp')
| -rw-r--r-- | usrp2/udp/udp_wrapper.v | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/usrp2/udp/udp_wrapper.v b/usrp2/udp/udp_wrapper.v index 390abd0d5..f4c642615 100644 --- a/usrp2/udp/udp_wrapper.v +++ b/usrp2/udp/udp_wrapper.v @@ -1,7 +1,6 @@ module udp_wrapper - #(parameter BASE=0, - parameter RXFIFOSIZE=11) + #(parameter BASE=0) (input clk, input reset, input clear, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [18:0] rx_f19_data, input rx_f19_src_rdy_i, output rx_f19_dst_rdy_o, @@ -44,8 +43,8 @@ module udp_wrapper wire rx_int2_src_rdy, rx_int2_dst_rdy; wire [18:0] rx_int2_data; - wire rx_int3_src_rdy, rx_int3_dst_rdy; - wire [35:0] rx_int3_data; + //wire rx_int3_src_rdy, rx_int3_dst_rdy; + //wire [35:0] rx_int3_data; `ifdef USE_PROT_ENG prot_eng_rx #(.BASE(BASE+32)) prot_eng_rx @@ -68,15 +67,16 @@ module udp_wrapper fifo19_to_fifo36 fifo19_to_fifo36 (.clk(clk), .reset(reset), .clear(clear), .f19_datain(rx_int2_data), .f19_src_rdy_i(rx_int2_src_rdy), .f19_dst_rdy_o(rx_int2_dst_rdy), - .f36_dataout(rx_int3_data), .f36_src_rdy_o(rx_int3_src_rdy), .f36_dst_rdy_i(rx_int3_dst_rdy), + .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy_o), .f36_dst_rdy_i(rx_f36_dst_rdy_i), .debug(debug_state)); - + + /* fifo_cascade #(.WIDTH(36),.SIZE(RXFIFOSIZE)) eth0_rxfifo (.clk(clk), .reset(reset), .clear(clear), .datain(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy), .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i), .space(), .occupied() ); - +*/ /* assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i }, { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy}, |