Merge branch 'udp' into master_merge_take2

* udp: (67 commits)
  better test program for just the tx side
  fix typo, no functionality difference
  ignores
  move dsp settings regs to reclocked setting bus.  Works, gets us to within 18ps of passing timing
  reverting logic clean up which should have made timing better, but made it worse instead
  moved fifos around, now easier to see where they are and how big
  bigger fifo on UDP TX path, to possibly fix overruns on decim=4
  Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround
  pps and vita time debug pins
  ignore emacs backup files
  more debug for fixing E's
  better debug pins for going after cascading E's
  copy in wrong place
  copied over from quad radio
  just debug pin changes
  typo caused the tx udp chain to be disconnected
  moved into subdir
  speed up timing by ignoring the too_early error.  We'll need to FIXME this later
  Added set time and set time at next pps. Removed the old sync pps commands, they dont make sense to use anymore.
  moved around regs, added a bit to allow for alternate PPS source
  ...

1 files changed, 92 insertions, 0 deletions

diff --git a/usrp2/udp/udp_wrapper.v b/usrp2/udp/udp_wrapper.v
new file mode 100644
index 000000000..f4c642615
--- /dev/null
+++ b/usrp2/udp/udp_wrapper.v
@@ -0,0 +1,92 @@
+
+module udp_wrapper
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [18:0] rx_f19_data, input rx_f19_src_rdy_i, output rx_f19_dst_rdy_o,
+    output [18:0] tx_f19_data, output tx_f19_src_rdy_o, input tx_f19_dst_rdy_i,
+    
+    output [35:0] rx_f36_data, output rx_f36_src_rdy_o, input rx_f36_dst_rdy_i,
+    input [35:0] tx_f36_data, input tx_f36_src_rdy_i, output tx_f36_dst_rdy_o,
+    output [31:0] debug
+    );
+
+   wire 	 tx_int1_src_rdy, tx_int1_dst_rdy;
+   wire [18:0] 	 tx_int1_data;
+   
+   wire 	 tx_int2_src_rdy, tx_int2_dst_rdy;
+   wire [18:0] 	 tx_int2_data;
+   wire [31:0] 	 debug_state;
+   
+   // TX side
+   fifo36_to_fifo19 fifo36_to_fifo19
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy_i), .f36_dst_rdy_o(tx_f36_dst_rdy_o),
+      .f19_dataout(tx_int1_data), .f19_src_rdy_o(tx_int1_src_rdy), .f19_dst_rdy_i(tx_int1_dst_rdy) );
+
+   fifo_short #(.WIDTH(19)) shortfifo19_a
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(tx_int1_data), .src_rdy_i(tx_int1_src_rdy), .dst_rdy_o(tx_int1_dst_rdy),
+      .dataout(tx_int2_data), .src_rdy_o(tx_int2_src_rdy), .dst_rdy_i(tx_int2_dst_rdy),
+      .space(), .occupied() );
+     
+   prot_eng_tx #(.BASE(BASE)) prot_eng_tx
+     (.clk(clk), .reset(reset), .clear(clear),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .datain(tx_int2_data), .src_rdy_i(tx_int2_src_rdy), .dst_rdy_o(tx_int2_dst_rdy),
+      .dataout(tx_f19_data), .src_rdy_o(tx_f19_src_rdy_o), .dst_rdy_i(tx_f19_dst_rdy_i) );
+
+   // RX side
+   wire rx_int1_src_rdy, rx_int1_dst_rdy;
+   wire [18:0] rx_int1_data;
+      
+   wire rx_int2_src_rdy, rx_int2_dst_rdy;
+   wire [18:0] rx_int2_data;
+      
+   //wire        rx_int3_src_rdy, rx_int3_dst_rdy;
+   //wire [35:0] rx_int3_data;
+   
+`ifdef USE_PROT_ENG
+   prot_eng_rx #(.BASE(BASE+32)) prot_eng_rx
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o),
+      .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) );
+`else
+   fifo19_rxrealign fifo19_rxrealign
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o),
+      .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) );
+`endif // !`ifdef USE_PROT_ENG
+   
+   fifo_short #(.WIDTH(19)) shortfifo19_b
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_int1_data), .src_rdy_i(rx_int1_src_rdy), .dst_rdy_o(rx_int1_dst_rdy),
+      .dataout(rx_int2_data), .src_rdy_o(rx_int2_src_rdy), .dst_rdy_i(rx_int2_dst_rdy),
+      .space(), .occupied() );
+
+   fifo19_to_fifo36 fifo19_to_fifo36
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f19_datain(rx_int2_data), .f19_src_rdy_i(rx_int2_src_rdy), .f19_dst_rdy_o(rx_int2_dst_rdy),
+      .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy_o), .f36_dst_rdy_i(rx_f36_dst_rdy_i),
+      .debug(debug_state));
+
+   /*
+   fifo_cascade #(.WIDTH(36),.SIZE(RXFIFOSIZE)) eth0_rxfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy),
+      .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i),
+      .space(), .occupied() );
+*/
+   /*
+   assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i },
+		    { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy},
+		    { rx_int3_data[35:32], rx_f36_data[35:32] },
+		    { debug_state[1:0], rx_int1_data[18:16], rx_int2_data[18:16] } };
+    */
+
+   assign debug = { { 3'd0, tx_int1_src_rdy, tx_int1_dst_rdy, tx_int1_data[18:16] },
+		    { 3'd0, tx_int2_src_rdy, tx_int2_dst_rdy, tx_int2_data[18:16] },
+		    { tx_int2_data[15:8] },
+		    { tx_int2_data[7:0] } };
+   
+endmodule // udp_wrapper