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authorMatt Ettus <matt@ettus.com>2011-03-07 21:15:33 -0800
committerMatt Ettus <matt@ettus.com>2011-03-16 12:26:38 -0700
commit4f0b3bff9285eeb9cc5f761e5ce0b2a8f9b90d38 (patch)
treec7e56205073830651d9a35f69619c71a65f7f799 /usrp2/udp/ethtx_realign.v
parent74979af6a089c67ac6579cb08040aec305032018 (diff)
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prot eng should work, ethtx is a skeleton
Diffstat (limited to 'usrp2/udp/ethtx_realign.v')
-rw-r--r--usrp2/udp/ethtx_realign.v24
1 files changed, 24 insertions, 0 deletions
diff --git a/usrp2/udp/ethtx_realign.v b/usrp2/udp/ethtx_realign.v
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index 000000000..c98d34cf4
--- /dev/null
+++ b/usrp2/udp/ethtx_realign.v
@@ -0,0 +1,24 @@
+
+module ethtx_realign
+ (input clk, input reset, input clear,
+ input [35:0] datain, input src_rdy_i, output dst_rdy_o,
+ output [35:0] dataout, output src_rdy_o, input dst_rdy_i);
+
+ reg state;
+
+ wire eof_in = datain[33];
+ wire [1:0] occ_in = datain[35:34];
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= 0;
+ else if
+
+ assign dataout[15:0] = datain[31:16];
+ assign dataout[31:16] = stored;
+
+ always @(posedge clk)
+ stored <= datain[15:0];
+
+
+endmodule // ethtx_realign