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| author | Josh Blum <josh@joshknows.com> | 2013-03-14 17:49:57 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2013-03-14 17:49:57 -0700 |
| commit | a370cb47bbec9a237dfd50b5247d621cd8ab5f4e (patch) | |
| tree | 3bd27bfb1f263a221f055218cddda90c15553e02 /usrp2/top | |
| parent | 8d91709d43f8df717abc8e05967e63c60887cd87 (diff) | |
| download | uhd-a370cb47bbec9a237dfd50b5247d621cd8ab5f4e.tar.gz uhd-a370cb47bbec9a237dfd50b5247d621cd8ab5f4e.tar.bz2 uhd-a370cb47bbec9a237dfd50b5247d621cd8ab5f4e.zip | |
e100: switch to fixed length xfers
Diffstat (limited to 'usrp2/top')
| -rw-r--r-- | usrp2/top/E1x0/E1x0.v | 18 | ||||
| -rw-r--r-- | usrp2/top/E1x0/Makefile.E110 | 2 | ||||
| -rw-r--r-- | usrp2/top/E1x0/timing.ucf | 4 |
3 files changed, 17 insertions, 7 deletions
diff --git a/usrp2/top/E1x0/E1x0.v b/usrp2/top/E1x0/E1x0.v index 8efb056e9..44129ce92 100644 --- a/usrp2/top/E1x0/E1x0.v +++ b/usrp2/top/E1x0/E1x0.v @@ -59,10 +59,20 @@ module E1x0 wire clk_fpga; wire reset; - reg async_reset; - always @(negedge EM_CLK) begin - async_reset <= ~EM_NCS6 && ~EM_NWE && (EM_A[9:2] == 8'hff) && EM_D[0]; - end + reg por_rst; + reg [7:0] por_counter = 8'h0; + + always @(posedge clk_fpga) + if (por_counter != 8'h55) + begin + por_counter <= por_counter + 8'h1; + por_rst <= 1'b1; + end + else por_rst <= 1'b0; + + wire async_reset; + cross_clock_reader #(.WIDTH(1)) read_gpio_reset + (.clk(clk_fpga), .rst(por_rst), .in(cgen_sen_b & ~cgen_sclk), .out(async_reset)); IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110 index e5be8d2fa..329ab54ce 100644 --- a/usrp2/top/E1x0/Makefile.E110 +++ b/usrp2/top/E1x0/Makefile.E110 @@ -50,7 +50,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \ TOP_SRCS = \ ../B100/u1plus_core.v \ E1x0.v \ -E1x0.ucf \ +DCM_GPMC.v \ timing.ucf SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ diff --git a/usrp2/top/E1x0/timing.ucf b/usrp2/top/E1x0/timing.ucf index 7d3d9e090..b0e449298 100644 --- a/usrp2/top/E1x0/timing.ucf +++ b/usrp2/top/E1x0/timing.ucf @@ -14,8 +14,8 @@ INST "EM_NCS6" TNM = gpmc_net; INST "EM_NWE" TNM = gpmc_net; INST "EM_NOE" TNM = gpmc_net; -TIMEGRP "gpmc_net" OFFSET = IN 6 ns VALID 12 ns BEFORE "EM_CLK" FALLING; -TIMEGRP "gpmc_net_out" OFFSET = OUT 14 ns AFTER "EM_CLK" RISING; //2 clock cyc per read +TIMEGRP "gpmc_net" OFFSET = IN 5 ns VALID 10 ns BEFORE "EM_CLK" FALLING; +#TIMEGRP "gpmc_net_out" OFFSET = OUT 13 ns AFTER "EM_CLK" RISING; //2 clock cyc per read #constrain interrupt lines NET "overo_gpio144" MAXDELAY = 5.5 ns; #have space |