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authorJosh Blum <josh@joshknows.com>2012-01-28 12:21:15 -0800
committerJosh Blum <josh@joshknows.com>2012-01-28 12:21:15 -0800
commit9f9729993197839d8be950d69eca4456c8e41323 (patch)
tree05295d25202f6167c9c1a60f0ca059c8b01593f7 /usrp2/top
parent0ff51a352d13f2ce6c59c82c90e853720936c88f (diff)
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dsp rework: moved scale and round into ddc chain
16to8 engine now performs only a clip from 16->8
Diffstat (limited to 'usrp2/top')
-rw-r--r--usrp2/top/B100/u1plus_core.v2
-rw-r--r--usrp2/top/E1x0/u1e_core.v2
-rw-r--r--usrp2/top/N2x0/u2plus_core.v2
-rw-r--r--usrp2/top/USRP2/u2_core.v2
4 files changed, 4 insertions, 4 deletions
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index 126d899d5..c61d836d0 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -410,7 +410,7 @@ module u1plus_core
// Readback mux 32 -- Slave #7
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd8, 16'd1}; //major, minor
+ localparam compat_num = {16'd9, 16'd0}; //major, minor
wire [31:0] reg_test32;
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index bd7bd26f6..5bf78bad2 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -455,7 +455,7 @@ module u1e_core
// Readback mux 32 -- Slave #7
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd8, 16'd1}; //major, minor
+ localparam compat_num = {16'd9, 16'd0}; //major, minor
wire [31:0] reg_test32;
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index 63087842b..f3405e63a 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -435,7 +435,7 @@ module u2plus_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd8, 16'd2}; //major, minor
+ localparam compat_num = {16'd9, 16'd0}; //major, minor
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index f2ca1908b..6c1a418d5 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -441,7 +441,7 @@ module u2_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd8, 16'd3}; //major, minor
+ localparam compat_num = {16'd9, 16'd0}; //major, minor
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),