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| author | Josh Blum <josh@joshknows.com> | 2012-03-02 16:26:11 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-03-16 11:29:18 -0700 |
| commit | 63e71a29a65b793ed23a78dbdc162018897238a7 (patch) | |
| tree | 36ef38858bbe7427e1dc410a0503efda29618f7a /usrp2/top | |
| parent | 0d712ac8ac311f716bb6fc418a46abb79c71e3b4 (diff) | |
| download | uhd-63e71a29a65b793ed23a78dbdc162018897238a7.tar.gz uhd-63e71a29a65b793ed23a78dbdc162018897238a7.tar.bz2 uhd-63e71a29a65b793ed23a78dbdc162018897238a7.zip | |
fifo_ctrl: switched to medfifo and separate result fifo
Diffstat (limited to 'usrp2/top')
| -rw-r--r-- | usrp2/top/N2x0/Makefile.N210R3 | 2 | ||||
| -rw-r--r-- | usrp2/top/N2x0/Makefile.N210R4 | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/N2x0/Makefile.N210R3 b/usrp2/top/N2x0/Makefile.N210R3 index 411aa20f1..3ef769d3a 100644 --- a/usrp2/top/N2x0/Makefile.N210R3 +++ b/usrp2/top/N2x0/Makefile.N210R3 @@ -70,7 +70,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" "$(CUSTOM_DEFS)" +"Verilog Macros" " FIFO_CTRL_USE_TIME=1 $(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/N2x0/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4 index 44ce17b3f..315388586 100644 --- a/usrp2/top/N2x0/Makefile.N210R4 +++ b/usrp2/top/N2x0/Makefile.N210R4 @@ -71,7 +71,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)" +"Verilog Macros" "LVDS=1 FIFO_CTRL_USE_TIME=1 $(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" |