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authorMatt Ettus <matt@ettus.com>2011-04-14 14:42:40 -0700
committerMatt Ettus <matt@ettus.com>2011-05-26 17:31:22 -0700
commit37cffdd35ab72551696a8d36c16d501b6d502ff1 (patch)
tree48bb1ca0967c016aa6ca3d92ba9580febaea824e /usrp2/top
parentb51ef6e5a461dd4d1c42252e902bdbedfa5dc8a7 (diff)
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u1p: vita packet generator for testing purposes
Diffstat (limited to 'usrp2/top')
-rw-r--r--usrp2/top/u1plus/u1plus_core.v3
1 files changed, 2 insertions, 1 deletions
diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v
index a3755b722..6d6fa878c 100644
--- a/usrp2/top/u1plus/u1plus_core.v
+++ b/usrp2/top/u1plus/u1plus_core.v
@@ -108,7 +108,7 @@ module u1plus_core
.tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc),
- .test_rate(test_rate), .test_ctrl(test_ctrl),
+ .test_len(test_len), .test_rate(test_rate), .test_ctrl(test_ctrl),
.debug0(debug0), .debug1(debug1));
// /////////////////////////////////////////////////////////////////////////
@@ -258,6 +258,7 @@ module u1plus_core
assign test_ctrl = xfer_rate[11:8];
assign test_rate = xfer_rate[7:0];
+ assign test_len = reg_test[15:0];
assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board
assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;