wishbone bridge now with minimal functionality. Need to check

timing and handle wait states.

6 files changed, 49 insertions, 9 deletions

diff --git a/usrp2/top/u1e/.gitignore b/usrp2/top/u1e/.gitignore
index f8b57ea21..8d872713e 100644
--- a/usrp2/top/u1e/.gitignore
+++ b/usrp2/top/u1e/.gitignore
@@ -2,3 +2,5 @@
 build
 *.log
 *.cmd
+tb_u1e
+*.lxt
diff --git a/usrp2/top/u1e/README b/usrp2/top/u1e/README
new file mode 100644
index 000000000..14c7a4955
--- /dev/null
+++ b/usrp2/top/u1e/README
@@ -0,0 +1,4 @@
+
+make clean
+make sim
+./tb_u1e -lxt2
diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile
new file mode 100644
index 000000000..5e4db5c65
--- /dev/null
+++ b/usrp2/top/u1e/cmdfile
@@ -0,0 +1,19 @@
+
+# My stuff
+-y .
+-y ../../control_lib
+-y ../../control_lib/newfifo
+-y ../../sdr_lib
+-y ../../timing
+-y ../../coregen
+-y ../../gpmc
+
+# Models
+-y ../../models
+
+# Open Cores
+-y ../opencores/spi/rtl/verilog
++incdir+../opencores/spi/rtl/verilog
+-y ../opencores/i2c/rtl/verilog
++incdir+../opencores/i2c/rtl/verilog
+
diff --git a/usrp2/top/u1e/make.sim b/usrp2/top/u1e/make.sim
new file mode 100644
index 000000000..1c163884c
--- /dev/null
+++ b/usrp2/top/u1e/make.sim
@@ -0,0 +1,7 @@
+all: sim
+
+sim:	
+	iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e
+
+clean:
+	rm -f tb_u1e *.vcd *.lxt a.out
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
index 6e0c60e17..85d2b49f0 100644
--- a/usrp2/top/u1e/tb_u1e.v
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -6,8 +6,12 @@ module tb_u1e();
    wire [2:0] debug_led;
    wire [31:0] debug;
    wire [1:0] debug_clk;
-   
-   
+
+   initial begin
+      $dumpfile("tb_u1e.lxt");
+      $dumpvars(0,tb_u1e);
+   end
+    
    // GPMC
    wire       EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE;
    wire [15:0] EM_D;
@@ -15,11 +19,16 @@ module tb_u1e();
    wire [1:0]  EM_NBE;
    
    reg  clk_fpga = 0;
-   always #100 clk_fpga = ~clk_fpga;
+   always #15.625 clk_fpga = ~clk_fpga;
    
    u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
 		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
 		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
 		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+
+   gpmc_model gpmc_model
+     (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+      .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
+      .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
    
-endmodule // u1e
+endmodule // tb_u1e
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 2481549b2..b0edbb9b6 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -10,7 +10,7 @@ module u1e_core
    );
 
    // Debug circuitry
-   reg [31:0] 	ctr;
+   reg [31:0] 	ctr=0;
    always @(posedge clk_fpga)
      ctr <= ctr + 1;
    
@@ -37,7 +37,7 @@ module u1e_core
    assign wb_clk = clk_fpga;
    reg [15:0] 	reg_fast, reg_slow;
 
-   localparam [10:0] WB_ADR_REG_FAST = 36;
+   localparam [10:0] WB_ADR_REG_FAST = 11'd36;
    localparam [10:0] WB_ADR_REG_SLOW = 38;
    
    always @(posedge wb_clk)
@@ -47,6 +47,5 @@ module u1e_core
    assign wb_dat_miso = (wb_adr == WB_ADR_REG_FAST) ? reg_fast : 16'bx;
 
    assign wb_ack = wb_stb & wb_cyc;
-   
-   
-endmodule // u2plus
+      
+endmodule // u1e_core