dsp rework: integrated custom dsp module shells

12 files changed, 46 insertions, 22 deletions

diff --git a/usrp2/top/B100/Makefile.B100 b/usrp2/top/B100/Makefile.B100
index 90dd25942..442b0b579 100644
--- a/usrp2/top/B100/Makefile.B100
+++ b/usrp2/top/B100/Makefile.B100
@@ -21,6 +21,7 @@ include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../gpif/Makefile.srcs
+include ../../custom/Makefile.srcs
 
 ##################################################
 # Project Properties
@@ -50,7 +51,7 @@ SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
 $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
 $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
 $(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
-$(GPIF_SRCS)
+$(GPIF_SRCS) $(CUSTOM_SRCS)
 
 ##################################################
 # Process Properties
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index 64c8defb3..4cc9386ab 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -156,9 +156,10 @@ module u1plus_core
    wire [35:0] 	 vita_rx_data0;
    wire 	 vita_rx_src_rdy0, vita_rx_dst_rdy0;
    
-   ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0
+   ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
      (.clk(wb_clk),.rst(wb_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
       .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
       .debug() );
@@ -179,9 +180,10 @@ module u1plus_core
    wire [35:0] 	 vita_rx_data1;
    wire 	 vita_rx_src_rdy1, vita_rx_dst_rdy1;
    
-   ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1
+   ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
      (.clk(wb_clk),.rst(wb_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
       .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
       .debug() );
@@ -222,12 +224,13 @@ module u1plus_core
       .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
       .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
       .sample(sample_tx), .strobe(strobe_tx),
-      .underrun(underrun), .run(run_tx),
+      .underrun(tx_underrun_dsp), .run(run_tx),
       .debug(debug_vt));
 
-   duc_chain #(.BASE(SR_TX_DSP)) duc_chain
+   duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
       .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
       .debug() );
diff --git a/usrp2/top/E1x0/Makefile.E100 b/usrp2/top/E1x0/Makefile.E100
index 9b9a48911..397bac618 100644
--- a/usrp2/top/E1x0/Makefile.E100
+++ b/usrp2/top/E1x0/Makefile.E100
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../gpmc/Makefile.srcs
+include ../../custom/Makefile.srcs
 
 ##################################################
 # Project Properties
@@ -53,7 +54,7 @@ SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
 $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
 $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
 $(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
-$(GPMC_SRCS)
+$(GPMC_SRCS) $(CUSTOM_SRCS)
 
 ##################################################
 # Process Properties
diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110
index be2761baf..1f95954ae 100644
--- a/usrp2/top/E1x0/Makefile.E110
+++ b/usrp2/top/E1x0/Makefile.E110
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../gpmc/Makefile.srcs
+include ../../custom/Makefile.srcs
 
 ##################################################
 # Project Properties
@@ -53,7 +54,7 @@ SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
 $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
 $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
 $(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
-$(GPMC_SRCS)
+$(GPMC_SRCS) $(CUSTOM_SRCS)
 
 ##################################################
 # Process Properties
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index 2c3690b0a..9257e5541 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -161,9 +161,10 @@ module u1e_core
    wire [35:0] 	 vita_rx_data0;
    wire 	 vita_rx_src_rdy0, vita_rx_dst_rdy0;
    
-   ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0
+   ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
      (.clk(wb_clk),.rst(wb_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
       .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
       .debug() );
@@ -184,9 +185,10 @@ module u1e_core
    wire [35:0] 	 vita_rx_data1;
    wire 	 vita_rx_src_rdy1, vita_rx_dst_rdy1;
    
-   ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1
+   ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
      (.clk(wb_clk),.rst(wb_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
       .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
       .debug() );
@@ -227,10 +229,10 @@ module u1e_core
       .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
       .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
       .sample(sample_tx), .strobe(strobe_tx),
-      .underrun(underrun), .run(run_tx),
+      .underrun(tx_underrun_dsp), .run(run_tx),
       .debug(debug_vt));
 
-   duc_chain #(.BASE(SR_TX_DSP)) duc_chain
+   duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
diff --git a/usrp2/top/N2x0/Makefile.N200R3 b/usrp2/top/N2x0/Makefile.N200R3
index 9ed5ece00..7181e7d62 100644
--- a/usrp2/top/N2x0/Makefile.N200R3
+++ b/usrp2/top/N2x0/Makefile.N200R3
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
 
 
 ##################################################
@@ -52,7 +53,8 @@ u2plus.ucf
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
 $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
 $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
 
 ##################################################
 # Process Properties
diff --git a/usrp2/top/N2x0/Makefile.N200R4 b/usrp2/top/N2x0/Makefile.N200R4
index f8640224f..551f7a232 100644
--- a/usrp2/top/N2x0/Makefile.N200R4
+++ b/usrp2/top/N2x0/Makefile.N200R4
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
 
 
 ##################################################
@@ -53,7 +54,8 @@ u2plus.ucf
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
 $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
 $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
 
 ##################################################
 # Process Properties
diff --git a/usrp2/top/N2x0/Makefile.N210R3 b/usrp2/top/N2x0/Makefile.N210R3
index 2937dc409..2514600f4 100644
--- a/usrp2/top/N2x0/Makefile.N210R3
+++ b/usrp2/top/N2x0/Makefile.N210R3
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
 
 
 ##################################################
@@ -52,7 +53,8 @@ u2plus.ucf
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
 $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
 $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
 
 ##################################################
 # Process Properties
diff --git a/usrp2/top/N2x0/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4
index 39a2508f9..951df0c7c 100644
--- a/usrp2/top/N2x0/Makefile.N210R4
+++ b/usrp2/top/N2x0/Makefile.N210R4
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
 
 
 ##################################################
@@ -53,7 +54,8 @@ u2plus.ucf
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
 $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
 $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
 
 ##################################################
 # Process Properties
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index bd9cbf610..63087842b 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -582,9 +582,10 @@ module u2plus_core
    always @(posedge dsp_clk)
      run_rx0_d1 <= run_rx0;
    
-   ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0
+   ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
       .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
       .debug() );
@@ -605,9 +606,10 @@ module u2plus_core
    always @(posedge dsp_clk)
      run_rx1_d1 <= run_rx1;
    
-   ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1
+   ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
       .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
       .debug() );
@@ -672,9 +674,10 @@ module u2plus_core
       .clear_vita(clear_tx), //output internal vita clear signal
       .debug(debug_vt));
 
-   duc_chain #(.BASE(SR_TX_DSP)) duc_chain
+   duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
       .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
       .debug() );
diff --git a/usrp2/top/USRP2/Makefile b/usrp2/top/USRP2/Makefile
index 8ebb43639..adfaf06c4 100644
--- a/usrp2/top/USRP2/Makefile
+++ b/usrp2/top/USRP2/Makefile
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
 
 
 ##################################################
@@ -52,7 +53,8 @@ u2_rev3.ucf
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
 $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
 $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
 
 ##################################################
 # Process Properties
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index a83a68204..f2ca1908b 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -570,9 +570,10 @@ module u2_core
    always @(posedge dsp_clk)
      run_rx0_d1 <= run_rx0;
    
-   ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0
+   ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
       .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
       .debug() );
@@ -593,9 +594,10 @@ module u2_core
    always @(posedge dsp_clk)
      run_rx1_d1 <= run_rx1;
    
-   ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1
+   ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
       .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
       .debug() );
@@ -658,9 +660,10 @@ module u2_core
       .clear_vita(clear_tx), //output internal vita clear signal
       .debug(debug_vt));
 
-   duc_chain #(.BASE(SR_TX_DSP)) duc_chain
+   duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
       .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
       .debug() );