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| author | Josh Blum <josh@joshknows.com> | 2012-02-18 22:15:10 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-18 22:15:10 -0800 |
| commit | e230fefb32ad5ec2a861fdfef876da068a702b6a (patch) | |
| tree | 5dd47fad603f0700ac3d69f07aa81779eea38b35 /usrp2/top | |
| parent | 026f57d204efc03a421602eb40b572dd9c2d0d2f (diff) | |
| download | uhd-e230fefb32ad5ec2a861fdfef876da068a702b6a.tar.gz uhd-e230fefb32ad5ec2a861fdfef876da068a702b6a.tar.bz2 uhd-e230fefb32ad5ec2a861fdfef876da068a702b6a.zip | |
usrp2/nseries: added churn to meet timing
Added churn to readback mux on nseries to make n200r4 meet timing.
Also added churn to usrp2 for parallelism, but assigned to zero.
Diffstat (limited to 'usrp2/top')
| -rw-r--r-- | usrp2/top/N2x0/u2plus_core.v | 3 | ||||
| -rw-r--r-- | usrp2/top/USRP2/u2_core.v | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v index 378f212e4..369f01183 100644 --- a/usrp2/top/N2x0/u2plus_core.v +++ b/usrp2/top/N2x0/u2plus_core.v @@ -437,12 +437,13 @@ module u2plus_core //compatibility number -> increment when the fpga has been sufficiently altered localparam compat_num = {16'd9, 16'd0}; //major, minor + wire [31:0] churn = status; //tweak churn until timing meets! wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word00(churn),.word01(32'b0),.word02(32'b0),.word03(32'b0), .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]), .word11(vita_time[31:0]),.word12(compat_num),.word13({18'b0, button, 1'b0, clk_status, serdes_link_up, 10'b0}), diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index 9b26b98e1..6bf60fe58 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -443,12 +443,13 @@ module u2_core //compatibility number -> increment when the fpga has been sufficiently altered localparam compat_num = {16'd9, 16'd0}; //major, minor + wire [31:0] churn = 0; //tweak churn until timing meets! wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word00(churn),.word01(32'b0),.word02(32'b0),.word03(32'b0), .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]), .word11(vita_time[31:0]),.word12(compat_num),.word13({20'b0, clk_status, serdes_link_up, 10'b0}), |