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| author | Nick Foster <nick@nerdnetworks.org> | 2011-09-28 12:29:47 -0700 |
|---|---|---|
| committer | Nick Foster <nick@nerdnetworks.org> | 2011-09-28 12:29:47 -0700 |
| commit | a08af5a91e45fcb721d9aca54cdc05673e8d63e2 (patch) | |
| tree | 56876593c0580297c2570fc156b311c369783496 /usrp2/top | |
| parent | 5a475ae9f1a1cbd1a6718cdf92de1712537e46f6 (diff) | |
| download | uhd-a08af5a91e45fcb721d9aca54cdc05673e8d63e2.tar.gz uhd-a08af5a91e45fcb721d9aca54cdc05673e8d63e2.tar.bz2 uhd-a08af5a91e45fcb721d9aca54cdc05673e8d63e2.zip | |
E100: GPSDO serial port level conversion
Diffstat (limited to 'usrp2/top')
| -rw-r--r-- | usrp2/top/E1x0/u1e.ucf | 6 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e.v | 5 |
2 files changed, 9 insertions, 2 deletions
diff --git a/usrp2/top/E1x0/u1e.ucf b/usrp2/top/E1x0/u1e.ucf index 0c487a601..278fc289a 100644 --- a/usrp2/top/E1x0/u1e.ucf +++ b/usrp2/top/E1x0/u1e.ucf @@ -67,8 +67,10 @@ NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug ## Overo UART -#NET "overo_txd1" LOC = "C6" ; -#NET "overo_rxd1" LOC = "D6" ; +NET "overo_txd1" LOC = "C6" ; +NET "overo_rxd1" LOC = "D6" ; +NET "fpga_txd1" LOC = "AB9" ; +NET "fpga_rxd1" LOC = "AB8" ; ## FTDI UART to USB converter NET "FPGA_TXD" LOC = "G19" ; diff --git a/usrp2/top/E1x0/u1e.v b/usrp2/top/E1x0/u1e.v index ff2e08394..903ef7a6f 100644 --- a/usrp2/top/E1x0/u1e.v +++ b/usrp2/top/E1x0/u1e.v @@ -22,6 +22,7 @@ module u1e (input CLK_FPGA_P, input CLK_FPGA_N, // Diff output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, input debug_pb, output FPGA_TXD, input FPGA_RXD, + output fpga_txd1, input fpga_rxd1, input overo_txd1, output overo_rxd1, // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, @@ -59,6 +60,10 @@ module u1e clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); // ///////////////////////////////////////////////////////////////////////// + // UART level conversion + assign fpga_txd1 = overo_txd1; + assign overo_rxd1 = fpga_rxd1; + // SPI wire mosi, sclk, miso; assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; |