moved into subdir

41 files changed, 8358 insertions, 0 deletions

diff --git a/usrp2/top/.gitignore b/usrp2/top/.gitignore
new file mode 100644
index 000000000..bf1b77066
--- /dev/null
+++ b/usrp2/top/.gitignore
@@ -0,0 +1 @@
+/*.sav
diff --git a/usrp2/top/eth_test/.gitignore b/usrp2/top/eth_test/.gitignore
new file mode 100644
index 000000000..b30397081
--- /dev/null
+++ b/usrp2/top/eth_test/.gitignore
@@ -0,0 +1,43 @@
+/xst
+/_ngo
+/_xmsgs
+/*.stx
+/*.tspec
+/*.xml
+/*.gyd
+/*.ngr
+/*.tim
+/*.err
+/*.lso
+/*.bld
+/*.cmd_log
+/*.ise_ISE_Backup
+/*.mfd
+/*.vm6
+/*.syr
+/*.xst
+/*.csv
+/*.html
+/*.jed
+/*.pad
+/*.ng*
+/*.pnx
+/*.rpt
+/*.prj
+/*_html
+/*_log
+/*.lfp
+/*.bit
+/*.bin
+/*.vcd
+/*.unroutes
+/*.drc
+/*_map.*
+/*_guide.*
+/*.twr
+/*.twx
+/a.out
+/*.xpi
+/*_pad.txt
+/*.bgn
+/*.par
diff --git a/usrp2/top/eth_test/eth_sim_top.v b/usrp2/top/eth_test/eth_sim_top.v
new file mode 100644
index 000000000..640a4e60f
--- /dev/null
+++ b/usrp2/top/eth_test/eth_sim_top.v
@@ -0,0 +1,437 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Module Name:    u2_basic
+//////////////////////////////////////////////////////////////////////////////////
+
+module eth_sim_top
+  (// Clocks
+   input dsp_clk,
+   input wb_clk,
+   output clock_ready,
+   input clk_to_mac,
+   input pps_in,
+   
+   // Misc, debug
+   output led1,
+   output led2,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+
+   // Expansion
+   input exp_pps_in,
+   output exp_pps_out,
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output [7:0] GMII_TXD,
+   output GMII_TX_EN,
+   output GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   input PHY_RESETn,
+   input PHY_CLK,   // possibly use on-board osc
+
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output [15:0] ser_t,
+   output ser_tklsb,
+   output ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output cpld_start,
+   output cpld_mode,
+   output cpld_done,
+   input cpld_din,
+   input cpld_clk,
+   input cpld_detached,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_oen_a,
+   output adc_pdn_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_oen_b,
+   output adc_pdn_b,
+   
+   // DAC
+   output [15:0] dac_a,
+   output [15:0] dac_b,
+
+   // I2C
+   input scl_pad_i,
+   output scl_pad_o,
+   output scl_pad_oen_o,
+   input sda_pad_i,
+   output sda_pad_o,
+   output sda_pad_oen_o,
+   
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Generic SPI
+   output sclk,
+   output mosi,
+   input miso,
+   output sen_clk,
+   output sen_dac,
+   output sen_tx_db,
+   output sen_tx_adc,
+   output sen_tx_dac,
+   output sen_rx_db,
+   output sen_rx_adc,
+   output sen_rx_dac,
+   
+   // GPIO to DBoards
+   inout [15:0] io_tx,
+   inout [15:0] io_rx
+   );
+   
+   wire [7:0] 	set_addr;
+   wire [31:0] 	set_data;
+   wire 	set_stb;
+   
+   wire 	ram_loader_done;
+   wire 	ram_loader_rst, wb_rst, dsp_rst;
+
+   wire [31:0] 	ser_debug;
+   
+   //////////////////////////////////////////////////////////////////////////////////////////////////
+   // Wishbone Single Master INTERCON
+   parameter 	dw = 32;  // Data bus width
+   parameter 	aw = 16;  // Address bus width, for byte addressibility, 16 = 64K byte memory space
+   parameter 	sw = 4;   // Select width -- 32-bit data bus with 8-bit granularity.  
+      
+   wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i;
+   wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
+		 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i;
+   wire [aw-1:0] m0_adr, m1_adr, s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr;
+   wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, s5_sel, s6_sel, s7_sel;
+   wire 	 m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, s5_ack, s6_ack, s7_ack;
+   wire 	 m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, s5_stb, s6_stb, s7_stb;
+   wire 	 m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, s5_cyc, s6_cyc, s7_cyc;
+   wire 	 m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, s5_err, s6_err, s7_err;
+   wire 	 m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, s5_rty, s6_rty, s7_rty;
+   wire 	 m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, s7_we;
+   
+   wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01),
+		.s27_addr_w(4),.s2_addr(4'b1000),.s3_addr(4'b1001),.s4_addr(4'b1010),
+		.s5_addr(4'b1011),.s6_addr(4'b1100),.s7_addr(4'b1101),
+		.dw(dw),.aw(aw),.sw(sw)) wb_1master
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      
+      .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
+      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+      .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o	(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+      .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty),
+      .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o	(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+      .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty),
+      .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o	(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+      .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty),
+      .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o	(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+      .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty),
+      .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o	(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+      .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty),
+      .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o	(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+      .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty),
+      .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o	(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+      .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty),
+      .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o	(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+      .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty)
+      );
+   
+   //////////////////////////////////////////////////////////////////////////////////////////
+   // Reset Controller
+   system_control sysctrl (.wb_clk_i(wb_clk),
+			   .ram_loader_rst_o(ram_loader_rst),
+			   .wb_rst_o(wb_rst),
+			   .ram_loader_done_i(ram_loader_done));
+   
+   // ///////////////////////////////////////////////////////////////////
+   // RAM Loader
+   wire 	 iram_wr_stb, iram_rd_stb, iram_wr_ack, iram_rd_ack, iram_ack, iram_wr_we;
+   wire [3:0] 	 iram_wr_sel;
+   wire [aw-1:0] iram_wr_adr, iram_rd_adr;
+   wire [dw-1:0] iram_wr_dat, iram_rd_dat;
+
+   wire 	 bus_error, proc_int;
+
+   assign 	 iram_rd_ack = ram_loader_done ? iram_ack : 1'b0;
+   assign 	 iram_wr_ack = ram_loader_done ? 1'b0 : iram_ack;
+   
+   ram_loader #(.AWIDTH(16))
+     ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+		 // CPLD Interface
+		 .cfg_clk_i(cpld_clk),
+		 .cfg_data_i(cpld_din),
+		 .start_o(cpld_start),
+		 .mode_o(cpld_mode),
+		 .done_o(cpld_done),
+		 .detached_i(cpld_detached),
+		 // Wishbone Interface
+		 .wb_dat_o(iram_wr_dat),.wb_adr_o(iram_wr_adr),
+		 .wb_stb_o(iram_wr_stb),.wb_cyc_o(),.wb_sel_o(iram_wr_sel),
+		 .wb_we_o(iram_wr_we),.wb_ack_i(iram_wr_ack),
+		 .ram_loader_done_o(ram_loader_done));
+
+   // Processor
+   aeMB_core_BE #(.ISIZ(16),.DSIZ(16))
+     aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
+	   // Instruction Wishbone bus to I-RAM
+	   .iwb_stb_o(iram_rd_stb),.iwb_adr_o(iram_rd_adr),
+	   .iwb_dat_i(iram_rd_dat),.iwb_ack_i(iram_rd_ack),
+	   // Data Wishbone bus to system bus fabric
+	   .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
+	   .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
+	   // Interrupts and exceptions
+	   .sys_int_i(proc_int),.sys_exc_i(bus_error) );
+
+   assign 	 bus_error = m0_err | m0_rty;
+   assign	 proc_int = 1'b0;
+   
+   // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
+   // I-port connects directly to processor and ram loader
+   
+   ram_wb_harvard #(.AWIDTH(14))
+     ID_ram (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+	     
+	     .iwb_adr_i(ram_loader_done ? iram_rd_adr : iram_wr_adr),.iwb_dat_i(iram_wr_dat),.iwb_dat_o(iram_rd_dat),
+	     .iwb_we_i(iram_wr_we),.iwb_ack_o(iram_ack),.iwb_stb_i(ram_loader_done ? iram_rd_stb : iram_wr_stb),
+	     .iwb_sel_i(ram_loader_done ? 4'b1111 : iram_wr_sel),
+	     
+	     .dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i),
+	     .dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel));
+
+   assign 	 s0_err = 1'b0;
+   assign 	 s0_rty = 1'b0;
+
+   // Buffer Pool, slave #1
+   wire 	 rd0_read, rd0_ready, rd0_done, rd0_empty;
+   wire 	 rd1_read, rd1_ready, rd1_done, rd1_empty;
+   wire 	 rd2_read, rd2_ready, rd2_done, rd2_empty;
+   wire 	 rd3_read, rd3_ready, rd3_done, rd3_empty;
+   wire [31:0] 	 rd0_dat, rd1_dat, rd2_dat, rd3_dat;
+
+   wire 	 wr0_write, wr0_done, wr0_ready, wr0_full;
+   wire 	 wr1_write, wr1_done, wr1_ready, wr1_full;
+   wire 	 wr2_write, wr2_done, wr2_ready, wr2_full;
+   wire 	 wr3_write, wr3_done, wr3_ready, wr3_full;
+   wire [31:0] 	 wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+
+/*   
+   buffer_pool buffer_pool
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+      .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),   
+      .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty),
+   
+      .stream_clk(dsp_clk),.stream_rst(dsp_rst),
+      // Write Interfaces
+      .wr0_dat_i(),.wr0_write_i(),.wr0_done_i(),.wr0_ready_o(),.wr0_full_o(),
+      .wr1_dat_i(),.wr1_write_i(),.wr1_done_i(),.wr1_ready_o(),.wr1_full_o(),
+      .wr2_dat_i(),.wr2_write_i(),.wr2_done_i(),.wr2_ready_o(),.wr2_full_o(),
+      .wr3_dat_i(),.wr3_write_i(),.wr3_done_i(),.wr3_ready_o(),.wr3_full_o(),
+      // Read Interfaces
+      .rd0_dat_o(rd0_dat),.rd0_read_i(rd0_read),.rd0_done_i(),.rd0_ready_o(rd0_ready),.rd0_empty_o(rd0_empty),
+      .rd1_dat_o(rd1_dat),.rd1_read_i(rd1_read),.rd1_done_i(),.rd1_ready_o(rd1_ready),.rd1_empty_o(rd1_empty),
+      .rd2_dat_o(rd2_dat),.rd2_read_i(rd2_read),.rd2_done_i(),.rd2_ready_o(rd2_ready),.rd2_empty_o(rd2_empty),
+      .rd3_dat_o(rd3_dat),.rd3_read_i(rd3_read),.rd3_done_i(),.rd3_ready_o(rd3_ready),.rd3_empty_o(rd3_empty)
+      );
+*/
+   // SPI -- Slave #2
+   spi_top shared_spi
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i),
+      .wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),
+
+      .wb_err_o(s2_err),.wb_int_o(s2_int),
+      .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+      .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+
+   assign 	 s2_rty = 1'b0;
+   
+   // I2C -- Slave #3
+   i2c_master_top #(.ARST_LVL(1)) 
+     i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
+	  .wb_adr_i(s3_adr),.wb_dat_i(s3_dat_o),.wb_dat_o(s3_dat_i),
+	  .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+	  .wb_ack_o(s3_ack),.wb_inta_o(st_int),
+	  .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+	  .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+   
+   assign 	 s3_err = 1'b0;
+   assign 	 s3_rty = 1'b0;
+
+   // GPIOs -- Slave #4
+   wire 	 s4_ack_a, s4_ack_b, s4_ack_c, s4_ack_d;
+   assign 	 s4_ack = s4_ack_a | s4_ack_b | s4_ack_c | s4_ack_d;
+
+   simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(~wb_rst),
+		      .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[0]),.adr_i(s4_adr[2]),.we_i(s4_we),
+		      .dat_i(s4_dat_o[7:0]),.dat_o(s4_dat_i[7:0]),.ack_o(s4_ack_a),
+		      .gpio(/* io_tx[7:0]*/) );
+   
+   simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(~wb_rst),
+		      .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[1]),.adr_i(s4_adr[2]),.we_i(s4_we),
+		      .dat_i(s4_dat_o[15:8]),.dat_o(s4_dat_i[15:8]),.ack_o(s4_ack_b),
+		      .gpio(/* io_tx[15:8] */) );
+   
+   simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(~wb_rst),
+		      .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[2]),.adr_i(s4_adr[2]),.we_i(s4_we),
+		      .dat_i(s4_dat_o[23:16]),.dat_o(s4_dat_i[23:16]),.ack_o(s4_ack_c),
+		      .gpio(/* io_rx[7:0] */) );
+   
+   simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(~wb_rst),
+		      .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[3]),.adr_i(s4_adr[2]),.we_i(s4_we),
+		      .dat_i(s4_dat_o[31:24]),.dat_o(s4_dat_i[31:24]),.ack_o(s4_ack_d),
+		      .gpio(/* io_rx[15:8]*/) );
+
+   assign 	 s4_err = 1'b0;
+   assign 	 s4_rty = 1'b0;
+   
+   // Output control lines, SLAVE #5
+   wire [7:0] 	 clock_outs, serdes_outs, adc_outs, misc_outs;
+   assign 	 {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
+   assign 	 {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
+   assign 	 { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0];
+   assign 	 {led2, led1} = misc_outs[1:0];
+   
+   wb_output_pins32 control_lines
+     (.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s5_dat_o),.wb_dat_o(s5_dat_i),
+      .wb_we_i(s5_we),.wb_sel_i(s5_sel),.wb_stb_i(s5_stb),.wb_ack_o(s5_ack),.wb_cyc_i(s5_cyc),
+      .port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} )  );
+
+   assign 	 s5_err = 1'b0;
+   assign 	 s5_rty = 1'b0;
+
+   // Ethernet slave, #6
+   eth_wrapper eth_wrapper
+     (.Reset(wb_rst),.Clk_125M(),.Clk_user(stream_clk),.Clk_reg(wb_clk),.Speed(),
+      .Gtx_clk(GMII_GTX_CLK),.Rx_clk(GMII_RX_CLK),.Tx_clk(GMII_TX_CLK),//used only in MII mode
+      .Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),.Rx_er(GMII_RX_ER),
+      .Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),.Crs(GMII_CRS),.Col(GMII_COL),
+      .Mdio(MDIO),.Mdc(MDC),
+      // FIFO Interfaces
+      .wr_dat_o(),.wr_write_o(),.wr_done_o(),.wr_ready_i(),.wr_full_i(),
+      .rd_dat_i(),.rd_read_o(),.rd_done_o(),.rd_ready_i(),.rd_empty_i(),
+      // Wishbone
+      .wb_dat_i(s6_dat_o),.wb_dat_o(s6_dat_i),.wb_adr_i(s6_adr),.wb_stb_i(s6_stb),.wb_we_i(s6_we),.wb_ack_o(s6_ack)
+      );
+   
+   assign 	 s6_err = 1'b0;
+   assign 	 s6_rty = 1'b0;
+   
+   // Settings Bus -- Slave #7
+   settings_bus settings_bus
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
+      .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
+      .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
+   
+   assign 	 s7_err = 1'b0;
+   assign 	 s7_rty = 1'b0;
+   assign 	 s7_dat_i = 32'd0;
+
+   ///////////////////////////////////////////////////////////////////////////
+   // DSP
+   reg [13:0] 	 adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
+   reg 		 adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
+   
+   always @(posedge dsp_clk)
+     begin
+	adc_a_reg1 <= adc_a;
+	adc_a_reg2 <= adc_a_reg1;
+	adc_b_reg1 <= adc_b;
+	adc_b_reg2 <= adc_b_reg1;
+	adc_ovf_a_reg1 <= adc_ovf_a;
+	adc_ovf_a_reg2 <= adc_ovf_a_reg1;
+	adc_ovf_b_reg1 <= adc_ovf_b;
+	adc_ovf_b_reg2 <= adc_ovf_b_reg1;
+     end // always @ (posedge dsp_clk)
+   
+   dsp_core_rx dsp_core_rx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .rx_dat_o(wr1_dat),.rx_write_o(wr1_write),.rx_done_o(wr1_done),
+      .rx_ready_i(wr1_ready),.rx_full_i(wr1_full),
+      .overrun() );
+   
+   dsp_core_tx dsp_core_tx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .dac_a(dac_a),.dac_b(dac_b),
+      .tx_dat_i(rd1_dat),.tx_read_o(rd1_read),.tx_done_o(rd1_done),
+      .tx_ready_i(rd1_ready),.tx_empty_i(rd1_empty),
+      .underrun() );
+   
+   assign dsp_rst = wb_rst;
+
+   /////////////////////////////////////////////////////////////////////////////////////
+   // SERDES
+   serdes_tx serdes_tx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+      .fifo_data_i(rd0_dat),.fifo_read_o(rd0_read),.fifo_done_o(rd0_done),
+      .fifo_ready_i(rd0_ready),.fifo_empty_i(rd0_empty)
+      );
+
+   serdes_rx serdes_rx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+      .fifo_data_o(wr0_dat),.fifo_wr_o(wr0_write),.fifo_ready_i(wr0_ready),.fifo_done_i(wr0_done)
+      );
+   
+   // Debug Pins
+   wire [31:0]	debug1={{1'b0,ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst},
+   			{1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached},
+   			{8'hAF},
+   			{2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}};
+
+   wire [31:0]	debug_wb={{iram_wr_we,ram_loader_done,clock_ready,iram_wr_ack,iram_wr_stb,ram_loader_rst,wb_rst,dsp_rst},
+   			  {iram_rd_adr[15:8]},
+   			  {iram_rd_adr[7:0]},
+   			  {serdes_outs}};
+
+   assign 	io_rx = ser_debug[31:16];
+   assign 	io_tx = ser_debug[15:0];
+ 
+   assign 	debug = debug_wb;
+   
+   assign 	debug_clk[0] = wb_clk;
+   assign 	debug_clk[1] = dsp_clk;	
+   
+endmodule // eth_test
+
+
+// Local Variables:
+// verilog-library-directories:("." "subdir" "subdir2")
+// verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v")
+// verilog-library-extensions:(".v" ".h")
+// End:
diff --git a/usrp2/top/eth_test/eth_tb.v b/usrp2/top/eth_test/eth_tb.v
new file mode 100644
index 000000000..451ce1e7e
--- /dev/null
+++ b/usrp2/top/eth_test/eth_tb.v
@@ -0,0 +1,257 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+// Nearly everything is an input
+
+module eth_tb();
+   // Misc, debug
+   wire led1;
+   wire led2;
+   wire [31:0] debug;
+   wire [1:0]  debug_clk;
+   
+   // Expansion
+   wire        exp_pps_in;
+   wire        exp_pps_out;
+   
+   // GMII
+   //   GMII-CTRL
+   wire        GMII_COL;
+   wire        GMII_CRS;
+   
+   //   GMII-TX
+   wire [7:0]  GMII_TXD;
+   wire        GMII_TX_EN;
+   wire        GMII_TX_ER;
+   wire        GMII_GTX_CLK;
+   wire        GMII_TX_CLK;  // 100mbps clk
+   
+   //   GMII-RX
+   wire [7:0]  GMII_RXD;
+   wire        GMII_RX_CLK;
+   wire        GMII_RX_DV;
+   wire        GMII_RX_ER;
+   
+   //   GMII-Management
+   wire        MDIO;
+   wire        MDC;
+   wire        PHY_INTn;   // open drain
+   wire        PHY_RESETn;
+   wire        PHY_CLK;   // possibly use on-board osc
+   
+   // RAM
+   wire [17:0] RAM_D;
+   wire [18:0] RAM_A;
+   wire        RAM_CE1n;
+   wire        RAM_CENn;
+   wire        RAM_CLK;
+   wire        RAM_WEn;
+   wire        RAM_OEn;
+   wire        RAM_LDn;
+   
+   // SERDES
+   wire        ser_enable;
+   wire        ser_prbsen;
+   wire        ser_loopen;
+   wire        ser_rx_en;
+   
+   wire        ser_tx_clk;
+   wire [15:0] ser_t;
+   wire        ser_tklsb;
+   wire        ser_tkmsb;
+   
+   wire        ser_rx_clk;
+   wire [15:0] ser_r;
+   wire        ser_rklsb;
+   wire        ser_rkmsb;
+   
+   // CPLD interface
+   wire        cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done;
+      
+   // ADC
+   wire [13:0] adc_a;
+   wire        adc_ovf_a;
+   wire        adc_oen_a;
+   wire        adc_pdn_a;
+   
+   wire [13:0] adc_b;
+   wire        adc_ovf_b;
+   wire        adc_oen_b;
+   wire        adc_pdn_b;
+   
+   // DAC
+   wire [15:0] dac_a;
+   wire [15:0] dac_b;
+   
+   // I2C
+   wire        SCL;
+   wire        SDA;
+   
+   // Clock Gen Control
+   wire [1:0]  clk_en;
+   wire [1:0]  clk_sel;
+   wire        clk_func;        // FIXME is an input to control the 9510
+   wire        clk_status;
+   
+   // Clocks
+   reg        clk_fpga;
+   wire        clk_to_mac;
+   wire        pps_in;
+   
+   // Generic SPI
+   wire        sclk, mosi, miso;   
+   wire        sen_clk;
+   wire        sen_dac;
+   wire        sen_tx_db;
+   wire        sen_tx_adc;
+   wire        sen_tx_dac;
+   wire        sen_rx_db;
+   wire        sen_rx_adc;
+   wire        sen_rx_dac;
+   
+   // GPIO to DBoards
+   wire [15:0] io_tx;
+   wire [15:0] io_rx;
+   
+   wire        wb_clk, wb_rst;
+   wire        start, clock_ready;
+   
+   reg 	       aux_clk;
+
+   initial aux_clk= 1'b0;
+   always #25 aux_clk = ~aux_clk;
+   
+   initial clk_fpga = 1'bx;
+   initial #3007 clk_fpga = 1'b0;
+   always #7 clk_fpga = ~clk_fpga;
+
+
+   wire        div_clk;
+   reg [2:0]   div_ctr = 0;
+   
+   always @(posedge clk_fpga or negedge clk_fpga)
+     if(div_ctr==5)
+       div_ctr = 0;
+     else
+       div_ctr = div_ctr + 1;
+   assign      div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2);
+   
+   assign      dsp_clk = clk_fpga;
+   assign      wb_clk = clock_ready ? div_clk : aux_clk;
+
+   initial
+     $monitor($time, ,clock_ready);
+   
+   initial begin
+      $dumpfile("eth_tb.vcd");
+      $dumpvars(0,eth_tb);
+   end
+
+   initial #10000000 $finish;
+
+   cpld_model 
+     cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done),
+		 .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached));
+   
+   eth_sim_top eth_sim_top(.dsp_clk		(dsp_clk),
+			   .wb_clk            (wb_clk),
+			   .clock_ready	(clock_ready),
+			   .clk_to_mac	(clk_to_mac),
+			   .pps_in		(pps_in),
+			   .led1		(led1),
+			   .led2		(led2),
+			   .debug		(debug[31:0]),
+			   .debug_clk		(debug_clk[1:0]),
+			   .exp_pps_in	(exp_pps_in),
+			   .exp_pps_out	(exp_pps_out),
+			   .GMII_COL		(GMII_COL),
+			   .GMII_CRS		(GMII_CRS),
+			   .GMII_TXD		(GMII_TXD[7:0]),
+			   .GMII_TX_EN	(GMII_TX_EN),
+			   .GMII_TX_ER	(GMII_TX_ER),
+			   .GMII_GTX_CLK	(GMII_GTX_CLK),
+			   .GMII_TX_CLK	(GMII_TX_CLK),
+			   .GMII_RXD		(GMII_RXD[7:0]),
+			   .GMII_RX_CLK	(GMII_RX_CLK),
+			   .GMII_RX_DV	(GMII_RX_DV),
+			   .GMII_RX_ER	(GMII_RX_ER),
+			   .MDIO		(MDIO),
+			   .MDC		(MDC),
+			   .PHY_INTn		(PHY_INTn),
+			   .PHY_RESETn	(PHY_RESETn),
+			   .PHY_CLK		(PHY_CLK),
+			   .ser_enable	(ser_enable),
+			   .ser_prbsen	(ser_prbsen),
+			   .ser_loopen	(ser_loopen),
+			   .ser_rx_en		(ser_rx_en),
+			   .ser_tx_clk	(ser_tx_clk),
+			   .ser_t		(ser_t[15:0]),
+			   .ser_tklsb		(ser_tklsb),
+			   .ser_tkmsb		(ser_tkmsb),
+			   .ser_rx_clk	(ser_rx_clk),
+			   .ser_r		(ser_r[15:0]),
+			   .ser_rklsb		(ser_rklsb),
+			   .ser_rkmsb		(ser_rkmsb),
+			   .cpld_start	(cpld_start),
+			   .cpld_mode		(cpld_mode),
+			   .cpld_done		(cpld_done),
+			   .cpld_din		(cpld_din),
+			   .cpld_clk		(cpld_clk),
+			   .cpld_detached	(cpld_detached),
+			   .adc_a		(adc_a[13:0]),
+			   .adc_ovf_a		(adc_ovf_a),
+			   .adc_oen_a		(adc_oen_a),
+			   .adc_pdn_a		(adc_pdn_a),
+			   .adc_b		(adc_b[13:0]),
+			   .adc_ovf_b		(adc_ovf_b),
+			   .adc_oen_b		(adc_oen_b),
+			   .adc_pdn_b		(adc_pdn_b),
+			   .dac_a		(dac_a[15:0]),
+			   .dac_b		(dac_b[15:0]),
+			   .scl_pad_i		(scl_pad_i),
+			   .scl_pad_o		(scl_pad_o),
+			   .scl_pad_oen_o	(scl_pad_oen_o),
+			   .sda_pad_i		(sda_pad_i),
+			   .sda_pad_o		(sda_pad_o),
+			   .sda_pad_oen_o	(sda_pad_oen_o),
+			   .clk_en		(clk_en[1:0]),
+			   .clk_sel		(clk_sel[1:0]),
+			   .clk_func		(clk_func),
+			   .clk_status	(clk_status),
+			   .sclk		(sclk),
+			   .mosi		(mosi),
+			   .miso		(miso),
+			   .sen_clk		(sen_clk),
+			   .sen_dac		(sen_dac),
+			   .sen_tx_db		(sen_tx_db),
+			   .sen_tx_adc	(sen_tx_adc),
+			   .sen_tx_dac	(sen_tx_dac),
+			   .sen_rx_db		(sen_rx_db),
+			   .sen_rx_adc	(sen_rx_adc),
+			   .sen_rx_dac	(sen_rx_dac),
+			   .io_tx		(io_tx[15:0]),
+			   .io_rx		(io_rx[15:0]));
+   
+   // Experimental printf-like function
+   always @(posedge wb_clk)
+     begin
+	if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC000))
+	  $write("%x",eth_sim_top.m0_dat_i);
+	if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC100))
+	  $display("%x",eth_sim_top.m0_dat_i);
+	if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC004))
+	  $write("%c",eth_sim_top.m0_dat_i);
+	if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC104))
+	  $display("%c",eth_sim_top.m0_dat_i);
+	if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC008))
+	  $display("");
+     end
+	
+
+endmodule // u2_sim_top
+
+// Local Variables:
+// verilog-library-directories:("." "subdir" "subdir2")
+// verilog-library-files:("/home/matt/u2f/top/u2_basic/u2_basic.v")
+// verilog-library-extensions:(".v" ".h")
+// End:
diff --git a/usrp2/top/single_u2_sim/single_u2_sim.v b/usrp2/top/single_u2_sim/single_u2_sim.v
new file mode 100644
index 000000000..2a7b24849
--- /dev/null
+++ b/usrp2/top/single_u2_sim/single_u2_sim.v
@@ -0,0 +1,324 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module single_u2_sim();
+   // Misc, debug
+   wire [7:0] leds;
+   wire [31:0] debug;
+   wire [1:0]  debug_clk;
+   
+   // Expansion
+   wire        exp_pps_in;
+   wire        exp_pps_out;
+   
+   // GMII
+   //   GMII-CTRL
+   wire        GMII_COL;
+   wire        GMII_CRS;
+   
+   //   GMII-TX
+   wire [7:0]  GMII_TXD;
+   wire        GMII_TX_EN;
+   wire        GMII_TX_ER;
+   wire        GMII_GTX_CLK;
+   wire        GMII_TX_CLK;  // 100mbps clk
+   
+   //   GMII-RX
+   wire [7:0]  GMII_RXD;
+   wire        GMII_RX_CLK;
+   wire        GMII_RX_DV;
+   wire        GMII_RX_ER;
+   
+   //   GMII-Management
+   wire        MDIO;
+   wire        MDC;
+   wire        PHY_INTn;   // open drain
+   wire        PHY_RESETn;
+   wire        PHY_CLK;   // possibly use on-board osc
+   
+   // RAM
+   wire [17:0] RAM_D;
+   wire [18:0] RAM_A;
+   wire        RAM_CE1n;
+   wire        RAM_CENn;
+   wire        RAM_CLK;
+   wire        RAM_WEn;
+   wire        RAM_OEn;
+   wire        RAM_LDn;
+   
+   // SERDES
+   wire        ser_enable;
+   wire        ser_prbsen;
+   wire        ser_loopen;
+   wire        ser_rx_en;
+   
+   wire        ser_tx_clk;
+   wire [15:0] ser_t;
+   wire        ser_tklsb;
+   wire        ser_tkmsb;
+   
+   wire        ser_rx_clk;
+   wire [15:0] ser_r;
+   wire        ser_rklsb;
+   wire        ser_rkmsb;
+   
+   // CPLD interface
+   wire        cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done;
+      
+   // ADC
+   wire [13:0] adc_a;
+   wire        adc_ovf_a;
+   wire        adc_on_a,  adc_oe_a;
+   
+   wire [13:0] adc_b;
+   wire        adc_ovf_b;
+   wire        adc_on_b, adc_oe_b;
+   
+   // DAC
+   wire [15:0] dac_a;
+   wire [15:0] dac_b;
+   
+   // I2C
+   wire        SCL;
+   wire        SDA;
+   
+   // Clock Gen Control
+   wire [1:0]  clk_en;
+   wire [1:0]  clk_sel;
+   wire        clk_func;        // FIXME is an input to control the 9510
+   wire        clk_status;
+   
+   // Clocks
+   reg 	       clk_fpga;
+   reg 	       clk_to_mac;
+   wire        pps_in;
+   
+   // Generic SPI
+   wire        sclk, mosi, miso;   
+   wire        sen_clk;
+   wire        sen_dac;
+   wire        sen_tx_db;
+   wire        sen_tx_adc;
+   wire        sen_tx_dac;
+   wire        sen_rx_db;
+   wire        sen_rx_adc;
+   wire        sen_rx_dac;
+   
+   // GPIO to DBoards
+   wire [15:0] io_tx;
+   wire [15:0] io_rx;
+   
+   wire        wb_clk;
+   wire        start, clock_ready;
+   
+   reg 	       aux_clk;
+
+   initial aux_clk= 1'b0;
+   always #6 aux_clk = ~aux_clk;
+   
+   initial clk_fpga = 1'bx;
+   initial #3007 clk_fpga = 1'b0;
+   always #5 clk_fpga = ~clk_fpga;
+   
+   initial clk_to_mac = 0;
+   always #4 clk_to_mac = ~clk_to_mac;
+   
+   wire        div_clk, dsp_clk;
+   reg [7:0]   div_ctr = 0;
+   
+   assign      dsp_clk = clock_ready ? clk_fpga : aux_clk;
+   assign      wb_clk = div_clk;
+
+`define CLK_DIV_2 1
+//`define CLK_DIV_3
+
+`ifdef CLK_DIV_2
+   localparam  clock_divider = 4'd2;
+   always @(posedge dsp_clk)
+     div_ctr <= div_ctr + 1;
+   assign      div_clk = div_ctr[0];
+`endif
+
+`ifdef CLK_DIV_3
+   localparam  clock_divider = 2;
+   always @(posedge dsp_clk or negedge dsp_clk)
+     if(div_ctr == 5)
+       div_ctr <= 0;
+     else
+       div_ctr <= div_ctr + 1;
+   assign      div_clk = ((div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2));
+`endif
+   
+   initial
+     $monitor($time, ,clock_ready);
+
+   always #1000000 $monitor("Time in ns ",$time);
+   
+   initial begin
+      @(negedge cpld_done);
+      @(posedge cpld_done);
+      $dumpfile("single_u2_sim.lxt");
+      $dumpvars(0,single_u2_sim);
+   end
+
+   initial #10000000 $finish;
+
+   cpld_model 
+     cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done),
+		 .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached));
+     
+   serdes_model serdes_model
+     (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t),
+      .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r),
+      .even(0),.error(0) );
+
+   adc_model adc_model
+     (.clk(dsp_clk),.rst(0),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_on_a(adc_on_a),.adc_oe_a(adc_oe_a),
+      .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) );
+
+   wire [2:0] speed;
+   phy_sim phy_model
+     (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK),
+      .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD),
+      .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD),
+      .Crs(GMII_CRS), .Col(GMII_COL),
+      .Speed(speed), .Done(0) );
+   pullup p3(MDIO);
+   
+   miim_model miim_model
+     (.mdc_i(MDC),.mdio(MDIO),.phy_resetn_i(PHY_RESETn),.phy_clk_i(PHY_CLK),
+      .phy_intn_o(PHY_INTn),.speed_o(speed) );
+   
+   xlnx_glbl glbl (.GSR(),.GTS());
+
+   wire       RAM_MODE = 1'b0;
+   cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A),
+		    .bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn),
+		    .ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0),
+		    .oeb(RAM_OEn),.cenb(RAM_CENn),.mode(RAM_MODE) );
+   
+   M24LC024B eeprom_model(.A0(0),.A1(0),.A2(0),.WP(0),
+			  .SDA(SDA),.SCL(SCL),.RESET(0));
+
+   wire       scl_pad_i, scl_pad_o, scl_pad_oen_o;
+   wire       sda_pad_i, sda_pad_o, sda_pad_oen_o;
+   
+   pullup p1(SCL);
+   pullup p2(SDA);
+
+   assign     scl_pad_i = SCL;
+   assign     sda_pad_i = SDA;
+
+   assign     SCL = scl_pad_oen_o ? 1'bz : scl_pad_o;
+   assign     SDA = sda_pad_oen_o ? 1'bz : sda_pad_o;
+
+   // printf output
+   wire       uart_baud_o, uart_tx_o, uart_rx_i;
+   assign     uart_rx_i = 1'b1;
+   
+   uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o));
+   
+   // End the simulation
+   always @(posedge wb_clk)
+     if((u2_core.m0_we == 1'd1)&&(u2_core.m0_adr == 16'hC2F0))
+       begin
+	  $display($time, "Finish called.",);
+	  $finish;
+       end
+   
+   u2_core #(.RAM_SIZE(32768))
+            u2_core(.dsp_clk		(dsp_clk),
+		     .wb_clk            (wb_clk),
+		     .clock_ready	(clock_ready),
+		     .clk_to_mac	(clk_to_mac),
+		     .pps_in		(pps_in),
+		     .leds		(leds),
+		     .debug		(debug[31:0]),
+		     .debug_clk		(debug_clk[1:0]),
+		     .exp_pps_in	(exp_pps_in),
+		     .exp_pps_out	(exp_pps_out),
+		     .GMII_COL		(GMII_COL),
+		     .GMII_CRS		(GMII_CRS),
+		     .GMII_TXD		(GMII_TXD[7:0]),
+		     .GMII_TX_EN	(GMII_TX_EN),
+		     .GMII_TX_ER	(GMII_TX_ER),
+		     .GMII_GTX_CLK	(GMII_GTX_CLK),
+		     .GMII_TX_CLK	(GMII_TX_CLK),
+		     .GMII_RXD		(GMII_RXD[7:0]),
+		     .GMII_RX_CLK	(GMII_RX_CLK),
+		     .GMII_RX_DV	(GMII_RX_DV),
+		     .GMII_RX_ER	(GMII_RX_ER),
+		     .MDIO		(MDIO),
+		     .MDC		(MDC),
+		     .PHY_INTn		(PHY_INTn),
+		     .PHY_RESETn	(PHY_RESETn),
+		     .ser_enable	(ser_enable),
+		     .ser_prbsen	(ser_prbsen),
+		     .ser_loopen	(ser_loopen),
+		     .ser_rx_en		(ser_rx_en),
+		     .ser_tx_clk	(ser_tx_clk),
+		     .ser_t		(ser_t[15:0]),
+		     .ser_tklsb		(ser_tklsb),
+		     .ser_tkmsb		(ser_tkmsb),
+		     .ser_rx_clk	(ser_rx_clk),
+		     .ser_r		(ser_r[15:0]),
+		     .ser_rklsb		(ser_rklsb),
+		     .ser_rkmsb		(ser_rkmsb),
+		     .cpld_start	(cpld_start),
+		     .cpld_mode		(cpld_mode),
+		     .cpld_done		(cpld_done),
+		     .cpld_din		(cpld_din),
+		     .cpld_clk		(cpld_clk),
+		     .cpld_detached	(cpld_detached),
+		     .cpld_init_b       (1),
+		     .por               (0),
+		     .adc_a		(adc_a[13:0]),
+		     .adc_ovf_a		(adc_ovf_a),
+		     .adc_on_a		(adc_on_a),
+		     .adc_oe_a		(adc_oe_a),
+		     .adc_b		(adc_b[13:0]),
+		     .adc_ovf_b		(adc_ovf_b),
+		     .adc_on_b		(adc_on_b),
+		     .adc_oe_b		(adc_oe_b),
+		     .dac_a		(dac_a[15:0]),
+		     .dac_b		(dac_b[15:0]),
+		     .scl_pad_i		(scl_pad_i),
+		     .scl_pad_o		(scl_pad_o),
+		     .scl_pad_oen_o	(scl_pad_oen_o),
+		     .sda_pad_i		(sda_pad_i),
+		     .sda_pad_o		(sda_pad_o),
+		     .sda_pad_oen_o	(sda_pad_oen_o),
+		     .clk_en		(clk_en[1:0]),
+		     .clk_sel		(clk_sel[1:0]),
+		     .clk_func		(clk_func),
+		     .clk_status	(clk_status),
+		     .sclk		(sclk),
+		     .mosi		(mosi),
+		     .miso		(miso),
+		     .sen_clk		(sen_clk),
+		     .sen_dac		(sen_dac),
+		     .sen_tx_db		(sen_tx_db),
+		     .sen_tx_adc	(sen_tx_adc),
+		     .sen_tx_dac	(sen_tx_dac),
+		     .sen_rx_db		(sen_rx_db),
+		     .sen_rx_adc	(sen_rx_adc),
+		     .sen_rx_dac	(sen_rx_dac),
+		     .io_tx		(io_tx[15:0]),
+		     .io_rx		(io_rx[15:0]),
+		     .RAM_D             (RAM_D),
+		     .RAM_A             (RAM_A),
+		     .RAM_CE1n          (RAM_CE1n),
+		     .RAM_CENn          (RAM_CENn),
+		     .RAM_CLK           (RAM_CLK),
+		     .RAM_WEn           (RAM_WEn),
+		     .RAM_OEn           (RAM_OEn),
+		     .RAM_LDn           (RAM_LDn),
+		     .uart_tx_o         (uart_tx_o),
+		     .uart_rx_i         (uart_rx_i),
+		     .uart_baud_o       (uart_baud_o),
+		     .sim_mode          (1'b1),
+		     .clock_divider     (clock_divider)
+		     );
+
+endmodule // single_u2_sim
diff --git a/usrp2/top/tcl/ise_helper.tcl b/usrp2/top/tcl/ise_helper.tcl
new file mode 100644
index 000000000..fe9db87af
--- /dev/null
+++ b/usrp2/top/tcl/ise_helper.tcl
@@ -0,0 +1,89 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+proc set_props {process options} {
+	if ![string compare $options ""] {
+		return
+	}
+	set state 1
+	foreach opt $options {
+		if $state {
+			set key $opt
+			set state 0
+		} else {
+			puts ">>> Setting: $process\[$key\] = $opt" 
+			if ![string compare $process "Project"] {
+				project set $key $opt
+			} else {
+				project set $key $opt -process $process
+			}
+			set state 1	
+		}
+	}
+}
+
+if [file isfile $env(PROJ_FILE)] {
+	puts ">>> Opening project: $env(PROJ_FILE)"
+	project open $env(PROJ_FILE)
+} else {	
+	puts ">>> Creating project: $env(PROJ_FILE)"
+	project new $env(PROJ_FILE)
+	
+	##################################################
+	# Set the project properties
+	##################################################
+	set_props "Project" $env(PROJECT_PROPERTIES)
+	
+	##################################################
+	# Add the sources
+	##################################################
+	foreach source $env(SOURCES) {
+		set source $env(SOURCE_ROOT)$source
+		puts ">>> Adding source to project: $source"
+		xfile add $source
+	}
+	
+	##################################################
+	# Set the top level module
+	##################################################
+	project set top $env(TOP_MODULE)
+	
+	##################################################
+	# Set the process properties
+	##################################################
+	set_props "Synthesize - XST" $env(SYNTHESIZE_PROPERTIES)
+	set_props "Translate" $env(TRANSLATE_PROPERTIES)
+	set_props "Map" $env(MAP_PROPERTIES)
+	set_props "Place & Route" $env(PLACE_ROUTE_PROPERTIES)
+	set_props "Generate Post-Place & Route Static Timing" $env(STATIC_TIMING_PROPERTIES)
+	set_props "Generate Programming File" $env(GEN_PROG_FILE_PROPERTIES)
+	set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES)
+}
+
+if [string compare $env(PROCESS_RUN) ""] {
+	puts ">>> Running Process: $env(PROCESS_RUN)"
+	process run $env(PROCESS_RUN)
+}
+
+project close
+exit
+
+
diff --git a/usrp2/top/u2_core/.gitignore b/usrp2/top/u2_core/.gitignore
new file mode 100644
index 000000000..9728395c1
--- /dev/null
+++ b/usrp2/top/u2_core/.gitignore
@@ -0,0 +1,44 @@
+*~
+/xst
+/_ngo
+/_xmsgs
+/*.stx
+/*.tspec
+/*.xml
+/*.gyd
+/*.ngr
+/*.tim
+/*.err
+/*.lso
+/*.bld
+/*.cmd_log
+/*.ise_ISE_Backup
+/*.mfd
+/*.vm6
+/*.syr
+/*.xst
+/*.csv
+/*.html
+/*.jed
+/*.pad
+/*.ng*
+/*.pnx
+/*.rpt
+/*.prj
+/*_html
+/*_log
+/*.lfp
+/*.bit
+/*.bin
+/*.vcd
+/*.unroutes
+/*.drc
+/*_map.*
+/*_guide.*
+/*.twr
+/*.twx
+/a.out
+/*.xpi
+/*_pad.txt
+/*.bgn
+/*.par
diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v
new file mode 100644
index 000000000..f5cc55670
--- /dev/null
+++ b/usrp2/top/u2_core/u2_core.v
@@ -0,0 +1,827 @@
+// ////////////////////////////////////////////////////////////////////////////////
+// Module Name:    u2_core
+// ////////////////////////////////////////////////////////////////////////////////
+
+module u2_core
+  #(parameter RAM_SIZE=32768)
+  (// Clocks
+   input dsp_clk,
+   input wb_clk,
+   output clock_ready,
+   input clk_to_mac,
+   input pps_in,
+   
+   // Misc, debug
+   output [7:0] leds,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+
+   // Expansion
+   input exp_pps_in,
+   output exp_pps_out,
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output [7:0] GMII_TXD,
+   output GMII_TX_EN,
+   output GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output [15:0] ser_t,
+   output ser_tklsb,
+   output ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output cpld_start,
+   output cpld_mode,
+   output cpld_done,
+   input cpld_din,
+   input cpld_clk,
+   input cpld_detached,
+   output cpld_misc,
+   input cpld_init_b,
+   input por,
+   output config_success,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_on_a,
+   output adc_oe_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_on_b,
+   output adc_oe_b,
+   
+   // DAC
+   output [15:0] dac_a,
+   output [15:0] dac_b,
+
+   // I2C
+   input scl_pad_i,
+   output scl_pad_o,
+   output scl_pad_oen_o,
+   input sda_pad_i,
+   output sda_pad_o,
+   output sda_pad_oen_o,
+   
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Generic SPI
+   output sclk,
+   output mosi,
+   input miso,
+   output sen_clk,
+   output sen_dac,
+   output sen_tx_db,
+   output sen_tx_adc,
+   output sen_tx_dac,
+   output sen_rx_db,
+   output sen_rx_adc,
+   output sen_rx_dac,
+   
+   // GPIO to DBoards
+   inout [15:0] io_tx,
+   inout [15:0] io_rx,
+
+   // External RAM
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // Debug stuff
+   output uart_tx_o, 
+   input uart_rx_i,
+   output uart_baud_o,
+   input sim_mode,
+   input [3:0] clock_divider
+   );
+
+   localparam SR_BUF_POOL = 64;   // Uses 1 reg
+   localparam SR_UDP_SM   = 96;   // 64 regs
+   localparam SR_RX_DSP   = 160;  // 16
+   localparam SR_RX_CTRL  = 176;  // 16
+   localparam SR_TIME64   = 192;  //  3
+   localparam SR_TX_DSP   = 208;  // 16
+   localparam SR_TX_CTRL  = 224;  // 16
+   
+			 
+   wire [7:0] 	set_addr;
+   wire [31:0] 	set_data;
+   wire 	set_stb;
+   
+   wire 	ram_loader_done;
+   wire 	ram_loader_rst, wb_rst, dsp_rst;
+
+   wire [31:0] 	status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
+   wire 	bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
+
+   wire [31:0] 	debug_gpio_0, debug_gpio_1;
+   wire [31:0] 	atr_lines;
+
+   wire [31:0] 	debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
+		debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp;
+
+   wire [15:0] 	ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
+   wire 	ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
+   wire 	ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2;
+	
+   wire 	serdes_link_up;
+   wire 	epoch;
+   wire [31:0] 	irq;
+   wire [63:0] 	vita_time;
+   
+   // ///////////////////////////////////////////////////////////////////////////////////////////////
+   // Wishbone Single Master INTERCON
+   localparam 	dw = 32;  // Data bus width
+   localparam 	aw = 16;  // Address bus width, for byte addressibility, 16 = 64K byte memory space
+   localparam	sw = 4;   // Select width -- 32-bit data bus with 8-bit granularity.  
+   
+   wire [dw-1:0] m0_dat_o, m0_dat_i;
+   wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
+		 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
+		 s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o,
+		 sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o;
+   wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr;
+   wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel;
+   wire 	 m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack;
+   wire 	 m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb;
+   wire 	 m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc;
+   wire 	 m0_err, m0_rty;
+   wire 	 m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we;
+   
+   wb_1master #(.decode_w(6),
+		.s0_addr(6'b0000_00),.s0_mask(6'b100000),
+		.s1_addr(6'b1000_00),.s1_mask(6'b110000),
+ 		.s2_addr(6'b1100_00),.s2_mask(6'b111111),
+		.s3_addr(6'b1100_01),.s3_mask(6'b111111),
+		.s4_addr(6'b1100_10),.s4_mask(6'b111111),
+		.s5_addr(6'b1100_11),.s5_mask(6'b111111),
+		.s6_addr(6'b1101_00),.s6_mask(6'b111111),
+		.s7_addr(6'b1101_01),.s7_mask(6'b111111),
+		.s8_addr(6'b1101_10),.s8_mask(6'b111111),
+		.s9_addr(6'b1101_11),.s9_mask(6'b111111),
+		.sa_addr(6'b1110_00),.sa_mask(6'b111111),
+		.sb_addr(6'b1110_01),.sb_mask(6'b111111),
+		.sc_addr(6'b1110_10),.sc_mask(6'b111111),
+		.sd_addr(6'b1110_11),.sd_mask(6'b111111),
+		.se_addr(6'b1111_00),.se_mask(6'b111111),
+		.sf_addr(6'b1111_01),.sf_mask(6'b111111),
+		.dw(dw),.aw(aw),.sw(sw)) wb_1master
+     (.clk_i(wb_clk),.rst_i(wb_rst),       
+      .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
+      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+      .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o	(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+      .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
+      .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o	(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+      .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
+      .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o	(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+      .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
+      .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o	(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+      .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
+      .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o	(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+      .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
+      .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o	(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+      .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
+      .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o	(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+      .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
+      .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o	(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+      .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
+      .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o	(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
+      .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
+      .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o	(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
+      .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
+      .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
+      .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
+      .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
+      .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
+      .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
+      .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
+      .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
+      .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
+      .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
+      .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
+      .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0)  );
+   
+   //////////////////////////////////////////////////////////////////////////////////////////
+   // Reset Controller
+   system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por),
+			   .ram_loader_rst_o(ram_loader_rst),
+			   .wb_rst_o(wb_rst),
+			   .ram_loader_done_i(ram_loader_done));
+
+   assign 	 config_success = ram_loader_done;
+   reg 		 takeover = 0;
+
+   wire 	 cpld_start_int, cpld_mode_int, cpld_done_int;
+   
+   always @(posedge wb_clk)
+     if(ram_loader_done)
+       takeover = 1;
+   assign 	 cpld_misc = ~takeover;
+
+   wire 	 sd_clk, sd_csn, sd_mosi, sd_miso;
+   
+   assign 	 sd_miso = cpld_din;
+   assign 	 cpld_start = takeover ? sd_clk	: cpld_start_int;
+   assign 	 cpld_mode = takeover ? sd_csn : cpld_mode_int;
+   assign 	 cpld_done = takeover ? sd_mosi : cpld_done_int;
+   
+   // ///////////////////////////////////////////////////////////////////
+   // RAM Loader
+
+   wire [31:0] 	 ram_loader_dat, iwb_dat;
+   wire [15:0] 	 ram_loader_adr, iwb_adr;
+   wire [3:0] 	 ram_loader_sel;
+   wire 	 ram_loader_stb, ram_loader_we, ram_loader_ack;
+   wire 	 iwb_ack, iwb_stb;
+   ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
+     ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+		 // CPLD Interface
+		 .cfg_clk_i(cpld_clk),
+		 .cfg_data_i(cpld_din),
+		 .start_o(cpld_start_int),
+		 .mode_o(cpld_mode_int),
+		 .done_o(cpld_done_int),
+		 .detached_i(cpld_detached),
+		 // Wishbone Interface
+		 .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
+		 .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
+		 .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
+		 .ram_loader_done_o(ram_loader_done));
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Processor
+   aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
+     aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
+	   // Instruction Wishbone bus to I-RAM
+	   .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
+	   .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
+	   // Data Wishbone bus to system bus fabric
+	   .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
+	   .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
+	   // Interrupts and exceptions
+	   .sys_int_i(proc_int),.sys_exc_i(bus_error) );
+   
+   assign 	 bus_error = m0_err | m0_rty;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
+   // I-port connects directly to processor and ram loader
+
+   wire 	 flush_icache;
+   ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
+     sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+	     
+	     .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
+	     .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
+	     .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
+	     .ram_loader_done_i(ram_loader_done),
+	     
+	     .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
+	     .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
+	     
+	     .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
+	     .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
+	     .flush_icache(flush_icache));
+   
+   setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+					 .in(set_data),.out(),.changed(flush_icache));
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Buffer Pool, slave #1
+   wire 	 rd0_ready_i, rd0_ready_o;
+   wire 	 rd1_ready_i, rd1_ready_o;
+   wire 	 rd2_ready_i, rd2_ready_o;
+   wire 	 rd3_ready_i, rd3_ready_o;
+   wire [3:0] 	 rd0_flags, rd1_flags, rd2_flags, rd3_flags;
+   wire [31:0] 	 rd0_dat, rd1_dat, rd2_dat, rd3_dat;
+
+   wire 	 wr0_ready_i, wr0_ready_o;
+   wire 	 wr1_ready_i, wr1_ready_o;
+   wire 	 wr2_ready_i, wr2_ready_o;
+   wire 	 wr3_ready_i, wr3_ready_o;
+   wire [3:0] 	 wr0_flags, wr1_flags, wr2_flags, wr3_flags;
+   wire [31:0] 	 wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+   
+   buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+      .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),   
+      .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
+   
+      .stream_clk(dsp_clk), .stream_rst(dsp_rst),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .status(status),.sys_int_o(buffer_int),
+
+      .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
+      .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
+
+      // Write Interfaces
+      .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o),
+      .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o),
+      .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o),
+      .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o),
+      // Read Interfaces
+      .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o),
+      .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o),
+      .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o),
+      .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o)
+      );
+
+   wire [31:0] 	 status_enc;
+   priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // SPI -- Slave #2
+   spi_top shared_spi
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
+      .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
+      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int),
+      .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+      .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // I2C -- Slave #3
+   i2c_master_top #(.ARST_LVL(1)) 
+     i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
+	  .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
+	  .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+	  .wb_ack_o(s3_ack),.wb_inta_o(i2c_int),
+	  .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+	  .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+   assign 	 s3_dat_i[31:8] = 24'd0;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // GPIOs -- Slave #4
+   nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
+		 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
+		 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
+		 .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+		 .gpio( {io_tx,io_rx} ) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Buffer Pool Status -- Slave #5   
+   
+   reg [31:0] 	 cycle_count;
+   always @(posedge wb_clk)
+     if(wb_rst)
+       cycle_count <= 0;
+     else
+       cycle_count <= cycle_count + 1;
+   
+   wb_readback_mux buff_pool_status
+     (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
+      .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
+      
+      .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
+      .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
+      .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0),
+      .word11(32'b0),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count)
+      );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Ethernet MAC  Slave #6
+
+   wire [18:0] 	 rx_f19_data, tx_f19_data;
+   wire 	 rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy;
+   
+   simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
+     (.clk125(clk_to_mac),  .reset(wb_rst),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .sys_clk(dsp_clk),
+      .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
+      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
+      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
+      .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
+      .mdio(MDIO), .mdc(MDC),
+      .debug(debug_mac));
+
+   udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy),
+      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy),
+      .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy_o(wr2_ready_i), .rx_f36_dst_rdy_i(wr2_ready_o),
+      .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy_i(rd2_ready_o), .tx_f36_dst_rdy_o(rd2_ready_i),
+      .debug(debug_udp) );
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Settings Bus -- Slave #7
+   settings_bus settings_bus
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
+      .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
+      .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
+   
+   assign 	 s7_dat_i = 32'd0;
+
+   // Output control lines
+   wire [7:0] 	 clock_outs, serdes_outs, adc_outs;
+   assign 	 {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
+   assign 	 {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
+   assign 	 {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0];
+
+   wire 	 phy_reset;
+   assign 	 PHY_RESETn = ~phy_reset;
+   
+   setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
+				      .in(set_data),.out(clock_outs),.changed());
+   setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(serdes_outs),.changed());
+   setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(adc_outs),.changed());
+   setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(phy_reset),.changed());
+
+   // /////////////////////////////////////////////////////////////////////////
+   //  LEDS
+   //    register 8 determines whether leds are controlled by SW or not
+   //    1 = controlled by HW, 0 = by SW
+   //    In Rev3 there are only 6 leds, and the highest one is on the ETH connector
+   
+   wire [7:0] 	 led_src, led_sw;
+   wire [7:0] 	 led_hw = {clk_status,serdes_link_up};
+   
+   setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(led_sw),.changed());
+   setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+					  .in(set_data),.out(led_src),.changed());
+
+   assign 	 leds = (led_src & led_hw) | (~led_src & led_sw);
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Interrupt Controller, Slave #8
+
+   assign irq= {{8'b0},
+		{8'b0},
+		{4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
+		{pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
+   
+   pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
+	   .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
+	   .irq(irq) );
+ 	 
+   // /////////////////////////////////////////////////////////////////////////
+   // Master Timer, Slave #9
+
+   wire [31:0] 	 master_time;
+   timer timer
+     (.wb_clk_i(wb_clk),.rst_i(wb_rst),
+      .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
+      .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
+      .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // UART, Slave #10
+
+   simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart  // depth of 3 is 128 entries
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack),
+      .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i),
+      .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
+      .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // ATR Controller, Slave #11
+
+   wire 	 run_rx, run_tx;
+   reg 		 run_rx_d1;
+   always @(posedge dsp_clk)
+     run_rx_d1 <= run_rx;
+   
+   atr_controller atr_controller
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i),
+      .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack),
+      .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
+   
+   // //////////////////////////////////////////////////////////////////////////
+   // Time Sync, Slave #12 
+
+   reg 		 pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1;
+   always @(negedge dsp_clk) pps_negedge <= pps_in;
+   always @(posedge dsp_clk) pps_posedge <= pps_in;
+   always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge;
+   always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge;   
+   
+   wire 	 pps_o;
+   time_sync time_sync
+     (.wb_clk_i(wb_clk),.rst_i(wb_rst),
+      .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]),
+      .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack),
+      .sys_clk_i(dsp_clk),.master_time_o(master_time),
+      .pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
+      .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
+      .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // SD Card Reader / Writer, Slave #13
+
+   sd_spi_wb sd_spi_wb
+     (.clk(wb_clk),.rst(wb_rst),
+      .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
+      .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we),
+      .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]),
+      .wb_ack_o(sd_ack) );
+
+   assign sd_dat_i[31:8] = 0;
+
+   // /////////////////////////////////////////////////////////////////////////
+   // DSP RX
+   wire [31:0] 	 sample_rx, sample_tx;
+   wire 	 strobe_rx, strobe_tx;
+   wire 	 rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy;
+   wire [99:0] 	 rx_data;
+   wire [35:0] 	 rx1_data;
+   
+   dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
+      .debug(debug_rx_dsp) );
+
+   vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .vita_time(vita_time), .overrun(overrun),
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy));
+
+   vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy),
+      .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy),
+      .fifo_occupied(), .fifo_full(), .fifo_empty() );
+
+   fifo_cascade #(.WIDTH(36), .SIZE(10)) rx_fifo_cascade
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
+      .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
+
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // DSP TX
+
+   wire [35:0] 	 tx_data;
+   wire [99:0] 	 tx1_data;
+   wire 	 tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy;
+
+   wire [31:0] 	 debug_vtc, debug_vtd, debug_vt;
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(10)) tx_fifo_cascade
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i),
+      .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) );
+
+   vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
+      .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
+      .debug(debug_vtd) );
+
+   vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .vita_time(vita_time),.underrun(underrun),
+      .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+      .debug(debug_vtc) );
+   
+   assign debug_vt = debug_vtc | debug_vtd;
+   
+   dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+      .dac_a(dac_a),.dac_b(dac_b),
+      .debug(debug_tx_dsp) );
+
+   assign dsp_rst = wb_rst;
+
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // SERDES
+/*
+   serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+      .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o),
+      .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+      .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o),
+      .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
+      .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
+      .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
+*/
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // External RAM Interface
+
+   localparam PAGE_SIZE = 10;  // PAGE SIZE is in bytes, 10 = 1024 bytes
+
+   wire [15:0] bus2ram, ram2bus;
+   wire [15:0] bridge_adr;
+   wire [1:0]  bridge_sel;
+   wire        bridge_stb, bridge_cyc, bridge_we, bridge_ack;
+   
+   wire [19:0] page;
+   wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]};
+   setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				       .in(set_data),.out(page),.changed());
+
+   wb_bridge_16_32 bridge
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),
+      .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel),
+      .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack),
+      .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel),
+      .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack));
+
+   wb_zbt16_b wb_zbt16_b
+     (.clk(wb_clk),.rst(wb_rst),
+      .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel),
+      .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we),
+      .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn),
+      .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
+      .sram_mode(),.sram_zz() );
+
+   assign      RAM_CE1n = 0;
+   assign      RAM_D[17:16] = 2'bzz;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // VITA Timing
+
+   time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
+     (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .pps(pps_o), .vita_time(vita_time), .pps_int());
+   
+   // /////////////////////////////////////////////////////////////////////////////////////////
+   // Debug Pins
+   
+   // FIFO Level Debugging
+   reg [31:0]  host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo;
+   
+   always @(posedge dsp_clk)
+     serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]},
+			     {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
+
+   always @(posedge dsp_clk)
+     dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]},
+			     {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+   
+   always @(posedge dsp_clk)
+     host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]},
+			   {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
+   
+   always @(posedge dsp_clk)
+     dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]},
+			   {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+   
+   always @(posedge dsp_clk)
+     eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]},
+			{eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
+   
+   assign  debug_clk[0]  = GMII_RX_CLK; // wb_clk;
+   assign  debug_clk[1]  = dsp_clk;
+
+/*
+ 
+   wire        mdio_cpy  = MDIO;
+   assign  debug 	 = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] },
+			     { s6_adr[15:8] },
+			     { s6_adr[7:0] },
+			     { 6'd0, mdio_cpy, MDC } };
+*/
+/*
+   assign debug 	 = { { GMII_TXD },
+			     { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK },
+			     { wr2_flags, rd2_flags },
+			     { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
+   assign debug 	 = { { GMII_RXD },
+			     { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK },
+			     { wr2_flags, rd2_flags },
+			     { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
+ */
+
+   assign debug = debug_udp;
+   assign debug_gpio_0 = debug_mac;
+   assign debug_gpio_1 = { rx_f19_src_rdy, rx_f19_dst_rdy, rx_f19_data };
+   
+endmodule // u2_core
+
+//   wire        debug_mux;
+//   setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+//					.in(set_data),.out(debug_mux),.changed());
+
+//assign     debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
+//assign     debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo;
+   
+//assign      debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
+//		{run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
+
+//assign      debug = debug_tx_dsp;
+//assign      debug = debug_serdes0;
+
+//assign      debug_gpio_0 = 0; //debug_serdes0;
+//assign      debug_gpio_1 = 0; //debug_serdes1;
+
+//   assign      debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success},
+//	      {8'b0},
+//      {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done },
+//    {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} };
+
+//assign      debug = {dac_a,dac_b};
+
+/*
+ assign      debug = {{ram_loader_done, takeover, 6'd0},
+ {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi},
+ {8'd0},
+ {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */
+
+/*assign      debug = host_to_dsp_fifo;
+ assign      debug_gpio_0 = eth_mac_debug;
+ assign      debug_gpio_1 = 0;
+ */
+// Assign various commonly used debug buses.
+/*
+ wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
+ irq[7:0],
+ GMII_RXD,
+ GMII_TXD};
+ 
+ wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
+   
+   wire [31:0] debug_time =  {uart_tx_o, 7'b0,
+			      irq[7:0],
+			      6'b0, GMII_RX_DV, GMII_TX_EN,
+			      4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int};
+
+   wire [31:0] debug_irq =  {uart_tx_o, iwb_adr, iwb_ack,
+			     irq[7:0],
+			     proc_int,  7'b0 };
+
+   wire [31:0] debug_eth = 
+	       {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
+		{8'd0},
+		{8'd0},
+		{GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} };
+
+   assign      debug_serdes0 = { { rd0_dat[7:0] },
+				 { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done },
+				 { ser_t[15:8] },
+				 { ser_t[7:0] } };
+
+   assign      debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write},
+				 { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en },
+				 { ser_r[15:8] },
+				 { ser_r[7:0] } };
+       
+   assign      debug_gpio_1 = {uart_tx_o,7'd0,
+			       3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error,
+			       debug_txc[15:0]};
+   assign      debug_gpio_1 = debug_rx;
+   assign      debug_gpio_1 = debug_serdes1;
+   assign      debug_gpio_1 = debug_eth;
+      
+    */
+      
diff --git a/usrp2/top/u2_rev1/.gitignore b/usrp2/top/u2_rev1/.gitignore
new file mode 100644
index 000000000..de5b50277
--- /dev/null
+++ b/usrp2/top/u2_rev1/.gitignore
@@ -0,0 +1,52 @@
+/templates
+/netgen
+/_ngo
+/_xmsgs
+/_pace.ucf
+/*.cmd
+/*.ibs
+/*.lfp
+/*.mfp
+/*.bit
+/*.bin
+/*.stx
+/*.par
+/*.unroutes
+/*.ntrc_log
+/*.ngr
+/*.mrp
+/*.html
+/*.lso
+/*.twr
+/*.bld
+/*.ncd
+/*.txt
+/*.cmd_log
+/*.drc
+/*.map
+/*.twr
+/*.xml
+/*.syr
+/*.ngm
+/*.xst
+/*.csv
+/*.html
+/*.lock
+/*.ncd
+/*.twx
+/*.ise_ISE_Backup
+/*.xml
+/*.ut
+/*.xpi
+/*.ngd
+/*.ncd
+/*.pad
+/*.bgn
+/*.ngc
+/*.pcf
+/*.ngd
+/xst
+/*.log
+/*.rpt
+/*.cel
+/*.restore
diff --git a/usrp2/top/u2_rev1/Makefile b/usrp2/top/u2_rev1/Makefile
new file mode 100644
index 000000000..b3245d883
--- /dev/null
+++ b/usrp2/top/u2_rev1/Makefile
@@ -0,0 +1,129 @@
+FILENAME=u2_fpga_top
+PARTNUM=xc3s1500-5fg456
+
+all: project command xst ngd ncd ncd2 bit 
+
+xst: 
+	xst -ifn ${FILENAME}.cmd -ofn xst.log
+
+ngd: 
+	ngdbuild -nt timestamp -p ${PARTNUM} ${FILENAME}
+
+ncd: 
+	rm -rf ${FILENAME}.ncd
+	map -detail -cm speed -k 8 -retiming on -equivalent_register_removal on -timing -ol high -pr b -p ${PARTNUM} ${FILENAME}.ngd -o ${FILENAME}.ncd ${FILENAME}.pcf
+
+# Place and route ncd file into new ncd file
+ncd2:	
+	par -ol high -xe n -w ${FILENAME}.ncd ${FILENAME} ${FILENAME}.pcf
+
+bit:	
+	bitgen -w ${FILENAME}.ncd -b ${FILENAME}.bit
+
+clean:
+	@rm -rf ${FILENAME}.ngc *.lst *.bit *.lso *.xst *.stx *.syr \
+	*.ngr *.cmd_log _ngc _xmsgs xst *.html *.srp \
+	*.blc *.bld *.ise_ISE_Backup *~ \
+	*.pad *.ngm *.ngd *.par *.pcf *.unroutes     \
+	*.xpi *.bgn *.drc *.bin *.mrp *.csv *.txt    \
+	*.rbt *.ncd ${FILENAME} *_cg templates/ tmp/ \
+        output.dat coregen.log *.ngo *.log ${FILENAME}.map \
+	${FILENAME}_summary.xml ${FILENAME}_usage.xml ${FILENAME}.twr
+
+command:
+	rm -rf ${FILENAME}.cmd
+	@echo "identification"       >> ${FILENAME}.cmd
+	@echo "status"               >> ${FILENAME}.cmd
+	@echo "time short"           >> ${FILENAME}.cmd
+	@echo "memory on"            >> ${FILENAME}.cmd
+	@echo "run "	             >> ${FILENAME}.cmd
+	@echo "-top ${FILENAME}"     >> ${FILENAME}.cmd
+	@echo "-ifn ${FILENAME}.prj" >> ${FILENAME}.cmd
+	@echo "-ifmt Verilog "       >> ${FILENAME}.cmd
+	@echo "-ofn ${FILENAME} "    >> ${FILENAME}.cmd
+	@echo "-p ${PARTNUM}"        >> ${FILENAME}.cmd
+	@echo "-bufg 6"              >> ${FILENAME}.cmd
+	@echo "-vlgincdir { ../../opencores/i2c/rtl/verilog ../../eth/rtl/verilog/ ../../opencores/spi/rtl/verilog}"  >> ${FILENAME}.cmd
+
+project:
+	rm -f ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/TECH/duram.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/sign_extend.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/cordic_stage.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/cic_int_shifter.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/cic_dec_shifter.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" '   	>> ${FILENAME}.prj
+	@echo '`include "../../opencores/aemb/rtl/verilog/aeMB_regfile.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/aemb/rtl/verilog/aeMB_fetch.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/aemb/rtl/verilog/aeMB_decode.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/aemb/rtl/verilog/aeMB_control.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/aemb/rtl/verilog/aeMB_aslu.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/miim/eth_shiftreg.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/miim/eth_outputcontrol.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/miim/eth_clockgen.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/TECH/eth_clk_switch.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/TECH/eth_clk_div2.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/Reg_int.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/RMON/RMON_dpram.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/RMON/RMON_ctrl.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_tx/flow_ctrl.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_tx/Ramdon_gen.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_tx/CRC_gen.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/ram_2port.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/cordic.v" '   					>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/cic_interp.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/cic_decim.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../opencores/spi/rtl/verilog/spi_shift.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/spi/rtl/verilog/spi_clgen.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" '   	>> ${FILENAME}.prj
+	@echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/eth_miim.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/RMON.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/Phy_int.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_tx.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_rx.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/Clk_ctrl.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/strobe_gen.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/ss_rcvr.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/shortfifo.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/setting_reg.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/mux8.v" '   					>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/mux4.v" '   					>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/longfifo.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/decoder_3_8.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/buffer_int.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/CRC16_D16.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/tx_control.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/rx_control.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/dsp_core_tx.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/dsp_core_rx.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../opencores/spi/rtl/verilog/spi_top.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/simple_pic/rtl/simple_pic.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_top.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_top.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/mac_txfifo_int.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/mac_rxfifo_int.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/wb_readback_mux.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/wb_1master.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/timer.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/system_control.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/settings_bus.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/serdes_tx.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/serdes_rx.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/ram_wb_harvard.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/ram_loader.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/nsgpio.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/buffer_pool.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../u2_basic/u2_basic.v" '   					>> ${FILENAME}.prj
+	@echo '`include "u2_fpga_top.v" '   						>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/elastic_buffer.v" '   			>> ${FILENAME}.prj
diff --git a/usrp2/top/u2_rev1/u2_fpga.ise b/usrp2/top/u2_rev1/u2_fpga.ise
new file mode 100644
index 000000000..f90caf024
--- /dev/null
+++ b/usrp2/top/u2_rev1/u2_fpga.ise
diff --git a/usrp2/top/u2_rev1/u2_fpga.ucf b/usrp2/top/u2_rev1/u2_fpga.ucf
new file mode 100755
index 000000000..5d2124819
--- /dev/null
+++ b/usrp2/top/u2_rev1/u2_fpga.ucf
@@ -0,0 +1,341 @@
+NET "adc_a[0]"  LOC = "A14"  ;
+NET "adc_a[10]"  LOC = "D20"  ;
+NET "adc_a[11]"  LOC = "D19"  ;
+NET "adc_a[12]"  LOC = "D21"  ;
+NET "adc_a[13]"  LOC = "E18"  ;
+NET "adc_a[1]"  LOC = "B14"  ;
+NET "adc_a[2]"  LOC = "C13"  ;
+NET "adc_a[3]"  LOC = "D13"  ;
+NET "adc_a[4]"  LOC = "A13"  ;
+NET "adc_a[5]"  LOC = "B13"  ;
+NET "adc_a[6]"  LOC = "E12"  ;
+NET "adc_a[7]"  LOC = "C22"  ;
+NET "adc_a[8]"  LOC = "C20"  ;
+NET "adc_a[9]"  LOC = "C21"  ;
+NET "adc_b[0]"  LOC = "A12"  ;
+NET "adc_b[10]"  LOC = "D18"  ;
+NET "adc_b[11]"  LOC = "B18"  ;
+NET "adc_b[12]"  LOC = "D17"  ;
+NET "adc_b[13]"  LOC = "E17"  ;
+NET "adc_b[1]"  LOC = "E16"  ;
+NET "adc_b[2]"  LOC = "F12"  ;
+NET "adc_b[3]"  LOC = "F13"  ;
+NET "adc_b[4]"  LOC = "F16"  ;
+NET "adc_b[5]"  LOC = "F17"  ;
+NET "adc_b[6]"  LOC = "C19"  ;
+NET "adc_b[7]"  LOC = "B20"  ;
+NET "adc_b[8]"  LOC = "B19"  ;
+NET "adc_b[9]"  LOC = "C18"  ;
+NET "clk_en[0]"  LOC = "C4"  ;
+NET "clk_en[1]"  LOC = "D1"  ;
+NET "clk_sel[0]"  LOC = "C3"  ;
+NET "clk_sel[1]"  LOC = "C2"  ;
+NET "dac_a[0]"  LOC = "A5"  ;
+NET "dac_a[10]"  LOC = "L2"  ;
+NET "dac_a[11]"  LOC = "L4"  ;
+NET "dac_a[12]"  LOC = "L3"  ;
+NET "dac_a[13]"  LOC = "L6"  ;
+NET "dac_a[14]"  LOC = "L5"  ;
+NET "dac_a[15]"  LOC = "K2"  ;
+NET "dac_a[1]"  LOC = "B5"  ;
+NET "dac_a[2]"  LOC = "C5"  ;
+NET "dac_a[3]"  LOC = "D5"  ;
+NET "dac_a[4]"  LOC = "A4"  ;
+NET "dac_a[5]"  LOC = "B4"  ;
+NET "dac_a[6]"  LOC = "F6"  ;
+NET "dac_a[7]"  LOC = "D10"  ;
+NET "dac_a[8]"  LOC = "D9"  ;
+NET "dac_a[9]"  LOC = "A10"  ;
+NET "dac_b[0]"  LOC = "D11"  ;
+NET "dac_b[10]"  LOC = "F9"  ;
+NET "dac_b[11]"  LOC = "A8"  ;
+NET "dac_b[12]"  LOC = "B8"  ;
+NET "dac_b[13]"  LOC = "D7"  ;
+NET "dac_b[14]"  LOC = "E7"  ;
+NET "dac_b[15]"  LOC = "B6"  ;
+NET "dac_b[1]"  LOC = "E11"  ;
+NET "dac_b[2]"  LOC = "F11"  ;
+NET "dac_b[3]"  LOC = "B10"  ;
+NET "dac_b[4]"  LOC = "C10"  ;
+NET "dac_b[5]"  LOC = "E10"  ;
+NET "dac_b[6]"  LOC = "F10"  ;
+NET "dac_b[7]"  LOC = "A9"  ;
+NET "dac_b[8]"  LOC = "B9"  ;
+NET "dac_b[9]"  LOC = "E9"  ;
+NET "debug[0]"  LOC = "N5"  ;
+NET "debug[10]"  LOC = "R4"  ;
+NET "debug[11]"  LOC = "T3"  ;
+NET "debug[12]"  LOC = "U3"  ;
+NET "debug[13]"  LOC = "M2"  ;
+NET "debug[14]"  LOC = "M3"  ;
+NET "debug[15]"  LOC = "M4"  ;
+NET "debug[16]"  LOC = "M5"  ;
+NET "debug[17]"  LOC = "M6"  ;
+NET "debug[18]"  LOC = "N1"  ;
+NET "debug[19]"  LOC = "N2"  ;
+NET "debug[1]"  LOC = "N6"  ;
+NET "debug[20]"  LOC = "N3"  ;
+NET "debug[21]"  LOC = "T1"  ;
+NET "debug[22]"  LOC = "T2"  ;
+NET "debug[23]"  LOC = "U2"  ;
+NET "debug[24]"  LOC = "T4"  ;
+NET "debug[25]"  LOC = "U4"  ;
+NET "debug[26]"  LOC = "T5"  ;
+NET "debug[27]"  LOC = "T6"  ;
+NET "debug[28]"  LOC = "U5"  ;
+NET "debug[29]"  LOC = "V5"  ;
+NET "debug[2]"  LOC = "P1"  ;
+NET "debug[30]"  LOC = "W2"  ;
+NET "debug[31]"  LOC = "W3"  ;
+NET "debug[3]"  LOC = "P2"  ;
+NET "debug[4]"  LOC = "P4"  ;
+NET "debug[5]"  LOC = "P5"  ;
+NET "debug[6]"  LOC = "R1"  ;
+NET "debug[7]"  LOC = "R2"  ;
+NET "debug[8]"  LOC = "P6"  ;
+NET "debug[9]"  LOC = "R5"  ;
+NET "debug_clk[0]"  LOC = "N4"  ;
+NET "debug_clk[1]"  LOC = "M1"  ;
+NET "GMII_RXD[0]"  LOC = "AA15"  ;
+NET "GMII_RXD[1]"  LOC = "AB15"  ;
+NET "GMII_RXD[2]"  LOC = "U14"  ;
+NET "GMII_RXD[3]"  LOC = "V14"  ;
+NET "GMII_RXD[4]"  LOC = "U13"  ;
+NET "GMII_RXD[5]"  LOC = "V13"  ;
+NET "GMII_RXD[6]"  LOC = "Y13"  ;
+NET "GMII_RXD[7]"  LOC = "AA13"  ;
+NET "GMII_TXD[0]"  LOC = "W14"  ;
+NET "GMII_TXD[1]"  LOC = "AA20"  ;
+NET "GMII_TXD[2]"  LOC = "AB20"  ;
+NET "GMII_TXD[3]"  LOC = "Y18"  ;
+NET "GMII_TXD[4]"  LOC = "AA18"  ;
+NET "GMII_TXD[5]"  LOC = "AB18"  ;
+NET "GMII_TXD[6]"  LOC = "V17"  ;
+NET "GMII_TXD[7]"  LOC = "W17"  ;
+NET "io_rx[0]"  LOC = "L21"  ;
+NET "io_rx[10]"  LOC = "F21"  ;
+NET "io_rx[11]"  LOC = "F20"  ;
+NET "io_rx[12]"  LOC = "G19"  ;
+NET "io_rx[13]"  LOC = "G18"  ;
+NET "io_rx[14]"  LOC = "G17"  ;
+NET "io_rx[15]"  LOC = "E22"  ;
+NET "io_rx[1]"  LOC = "L20"  ;
+NET "io_rx[2]"  LOC = "L19"  ;
+NET "io_rx[3]"  LOC = "L18"  ;
+NET "io_rx[4]"  LOC = "L17"  ;
+NET "io_rx[5]"  LOC = "K22"  ;
+NET "io_rx[6]"  LOC = "K21"  ;
+NET "io_rx[7]"  LOC = "K20"  ;
+NET "io_rx[8]"  LOC = "G22"  ;
+NET "io_rx[9]"  LOC = "G21"  ;
+NET "io_tx[0]"  LOC = "K4"  ;
+NET "io_tx[10]"  LOC = "E1"  ;
+NET "io_tx[11]"  LOC = "E3"  ;
+NET "io_tx[12]"  LOC = "F4"  ;
+NET "io_tx[13]"  LOC = "D2"  ;
+NET "io_tx[14]"  LOC = "D4"  ;
+NET "io_tx[15]"  LOC = "E4"  ;
+NET "io_tx[1]"  LOC = "K3"  ;
+NET "io_tx[2]"  LOC = "G1"  ;
+NET "io_tx[3]"  LOC = "G5"  ;
+NET "io_tx[4]"  LOC = "H5"  ;
+NET "io_tx[5]"  LOC = "F3"  ;
+NET "io_tx[6]"  LOC = "F2"  ;
+NET "io_tx[7]"  LOC = "F5"  ;
+NET "io_tx[8]"  LOC = "G6"  ;
+NET "io_tx[9]"  LOC = "E2"  ;
+NET "RAM_A[0]"  LOC = "N22"  ;
+NET "RAM_A[10]"  LOC = "P18"  ;
+NET "RAM_A[11]"  LOC = "R19"  ;
+NET "RAM_A[12]"  LOC = "P19"  ;
+NET "RAM_A[13]"  LOC = "R21"  ;
+NET "RAM_A[14]"  LOC = "R22"  ;
+NET "RAM_A[15]"  LOC = "T19"  ;
+NET "RAM_A[16]"  LOC = "T20"  ;
+NET "RAM_A[17]"  LOC = "U20"  ;
+NET "RAM_A[18]"  LOC = "W19"  ;
+NET "RAM_A[1]"  LOC = "N20"  ;
+NET "RAM_A[2]"  LOC = "T21"  ;
+NET "RAM_A[3]"  LOC = "M22"  ;
+NET "RAM_A[4]"  LOC = "N19"  ;
+NET "RAM_A[5]"  LOC = "N17"  ;
+NET "RAM_A[6]"  LOC = "N18"  ;
+NET "RAM_A[7]"  LOC = "P21"  ;
+NET "RAM_A[8]"  LOC = "P22"  ;
+NET "RAM_A[9]"  LOC = "P17"  ;
+NET "RAM_D[0]"  LOC = "Y21"  ;
+NET "RAM_D[10]"  LOC = "V22"  ;
+NET "RAM_D[11]"  LOC = "V21"  ;
+NET "RAM_D[12]"  LOC = "T17"  ;
+NET "RAM_D[13]"  LOC = "U18"  ;
+NET "RAM_D[14]"  LOC = "U21"  ;
+NET "RAM_D[15]"  LOC = "R18"  ;
+NET "RAM_D[16]"  LOC = "T18"  ;
+NET "RAM_D[17]"  LOC = "T22"  ;
+NET "RAM_D[1]"  LOC = "Y20"  ;
+NET "RAM_D[2]"  LOC = "Y19"  ;
+NET "RAM_D[3]"  LOC = "W22"  ;
+NET "RAM_D[4]"  LOC = "Y22"  ;
+NET "RAM_D[5]"  LOC = "V19"  ;
+NET "RAM_D[6]"  LOC = "W21"  ;
+NET "RAM_D[7]"  LOC = "W20"  ;
+NET "RAM_D[8]"  LOC = "U19"  ;
+NET "RAM_D[9]"  LOC = "V20"  ;
+NET "ser_r[0]"  LOC = "AB10"  ;
+NET "ser_r[10]"  LOC = "W10"  ;
+NET "ser_r[11]"  LOC = "Y1"  ;
+NET "ser_r[12]"  LOC = "Y3"  ;
+NET "ser_r[13]"  LOC = "Y2"  ;
+NET "ser_r[14]"  LOC = "W4"  ;
+NET "ser_r[15]"  LOC = "W1"  ;
+NET "ser_r[1]"  LOC = "AA10"  ;
+NET "ser_r[2]"  LOC = "U9"  ;
+NET "ser_r[3]"  LOC = "U6"  ;
+NET "ser_r[4]"  LOC = "AB11"  ;
+NET "ser_r[5]"  LOC = "Y7"  ;
+NET "ser_r[6]"  LOC = "W7"  ;
+NET "ser_r[7]"  LOC = "AB7"  ;
+NET "ser_r[8]"  LOC = "AA7"  ;
+NET "ser_r[9]"  LOC = "W9"  ;
+NET "ser_t[0]"  LOC = "V7"  ;
+NET "ser_t[10]"  LOC = "AA6"  ;
+NET "ser_t[11]"  LOC = "Y6"  ;
+NET "ser_t[12]"  LOC = "W8"  ;
+NET "ser_t[13]"  LOC = "V8"  ;
+NET "ser_t[14]"  LOC = "AB8"  ;
+NET "ser_t[15]"  LOC = "AA8"  ;
+NET "ser_t[1]"  LOC = "V10"  ;
+NET "ser_t[2]"  LOC = "AB4"  ;
+NET "ser_t[3]"  LOC = "AA4"  ;
+NET "ser_t[4]"  LOC = "Y5"  ;
+NET "ser_t[5]"  LOC = "W5"  ;
+NET "ser_t[6]"  LOC = "AB5"  ;
+NET "ser_t[7]"  LOC = "AA5"  ;
+NET "ser_t[8]"  LOC = "W6"  ;
+NET "ser_t[9]"  LOC = "V6"  ;
+NET "clk_muxed" TNM_NET = "clk_muxed";
+TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "adc_oen_a"  LOC = "E19"  ; 
+NET "adc_oen_b"  LOC = "C17"  ; 
+NET "adc_ovf_a"  LOC = "F18"  ; 
+NET "adc_ovf_b"  LOC = "B17"  ; 
+NET "adc_pdn_a"  LOC = "E20"  ; 
+NET "adc_pdn_b"  LOC = "D15"  ; 
+NET "clk_fpga_n"  LOC = "B11"  ; 
+NET "clk_fpga_p"  LOC = "A11"  ; 
+NET "clk_func"  LOC = "C12"  ; 
+NET "clk_status"  LOC = "B12"  ; 
+NET "clk_to_mac"  LOC = "AB12"  ; 
+NET "cpld_clk"  LOC = "AB14"  ; 
+NET "cpld_din"  LOC = "AA14"  ; 
+NET "cpld_done"  LOC = "V12"  ; 
+NET "cpld_mode"  LOC = "U12"  ; 
+NET "cpld_start"  LOC = "AA9"  ; 
+NET "exp_pps_in_n"  LOC = "V4"  ; 
+NET "exp_pps_in_p"  LOC = "V3"  ; 
+NET "exp_pps_out_n"  LOC = "V2"  ; 
+NET "exp_pps_out_p"  LOC = "V1"  ; 
+NET "GMII_COL"  LOC = "U16"  ; 
+NET "GMII_CRS"  LOC = "U17"  ; 
+NET "GMII_GTX_CLK"  LOC = "AA17" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "GMII_RX_CLK"  LOC = "W16"  ; 
+NET "GMII_RX_DV"  LOC = "AB16"  ; 
+NET "GMII_RX_ER"  LOC = "AA16"  ; 
+NET "GMII_TX_CLK"  LOC = "W13"  ; 
+NET "GMII_TX_EN"  LOC = "Y17" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "GMII_TX_ER"  LOC = "V16" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "GMII_TXD<0>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<1>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<2>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<3>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<4>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<5>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<6>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<7>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "led1"  LOC = "V11"  ; 
+NET "led2"  LOC = "Y12"  ; 
+NET "MDC"  LOC = "V18"  ; 
+NET "MDIO"  LOC = "Y16" | PULLUP ; 
+NET "PHY_CLK"  LOC = "V15"  ; 
+NET "PHY_INTn"  LOC = "AB13"  ; 
+NET "PHY_RESETn"  LOC = "AA19"  ; 
+NET "pps_in"  LOC = "Y11"  ; 
+NET "RAM_CE1n"  LOC = "N21"  ; 
+NET "RAM_CENn"  LOC = "M18"  ; 
+NET "RAM_CLK"  LOC = "M17"  ; 
+NET "RAM_LDn"  LOC = "M21"  ; 
+NET "RAM_OEn"  LOC = "M19"  ; 
+NET "RAM_WEn"  LOC = "M20"  ; 
+NET "SCL"  LOC = "A7"  ; 
+NET "SCL_force"  LOC = "E8"  ; 
+NET "sclk"  LOC = "K5"  ; 
+NET "sclk_rx_adc"  LOC = "J17"  ; 
+NET "sclk_rx_dac"  LOC = "J19"  ; 
+NET "sclk_rx_db"  LOC = "F19"  ; 
+NET "sclk_tx_adc"  LOC = "H1"  ; 
+NET "sclk_tx_dac"  LOC = "J5"  ; 
+NET "sclk_tx_db"  LOC = "D3"  ; 
+NET "SDA"  LOC = "D8"  ; 
+NET "SDA_force"  LOC = "C11"  ; 
+NET "sdi"  LOC = "J1"  ; 
+NET "sdi_rx_adc"  LOC = "H22"  ; 
+NET "sdi_rx_dac"  LOC = "J21"  ; 
+NET "sdi_rx_db"  LOC = "H19"  ; 
+NET "sdi_tx_adc"  LOC = "J4"  ; 
+NET "sdi_tx_dac"  LOC = "J6"  ; 
+NET "sdi_tx_db"  LOC = "G4"  ; 
+NET "sdo"  LOC = "J2"  ; 
+NET "sdo_rx_adc"  LOC = "H21"  ; 
+NET "sdo_rx_db"  LOC = "G20"  ; 
+NET "sdo_tx_adc"  LOC = "H2"  ; 
+NET "sdo_tx_db"  LOC = "G3"  ; 
+NET "sen_clk"  LOC = "K6"  ; 
+NET "sen_dac"  LOC = "L1"  ; 
+NET "sen_rx_adc"  LOC = "H18"  ; 
+NET "sen_rx_dac"  LOC = "J18"  ; 
+NET "sen_rx_db"  LOC = "D22"  ; 
+NET "sen_tx_adc"  LOC = "G2"  ; 
+NET "sen_tx_dac"  LOC = "H4"  ; 
+NET "sen_tx_db"  LOC = "C1"  ; 
+NET "ser_enable"  LOC = "W11"  ; 
+NET "ser_loopen"  LOC = "Y4"  ; 
+NET "ser_prbsen"  LOC = "AA3"  ; 
+NET "ser_rklsb"  LOC = "V9"  ; 
+NET "ser_rkmsb"  LOC = "Y10"  ; 
+NET "ser_rx_clk"  LOC = "AA11"  ; 
+NET "ser_rx_en"  LOC = "AB9"  ; 
+NET "ser_tklsb"  LOC = "U10" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "ser_tkmsb"  LOC = "U11" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "ser_tx_clk"  LOC = "U7" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "ser_t<0>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<1>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<2>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<3>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<4>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<5>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<6>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<7>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<8>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<9>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<10>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<11>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<12>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<13>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<14>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<15>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
diff --git a/usrp2/top/u2_rev1/u2_fpga_top.prj b/usrp2/top/u2_rev1/u2_fpga_top.prj
new file mode 100644
index 000000000..544415f4d
--- /dev/null
+++ b/usrp2/top/u2_rev1/u2_fpga_top.prj
@@ -0,0 +1,102 @@
+verilog work "../../opencores/uart16550/rtl/verilog/raminfr.v"
+verilog work "../../control_lib/ram_2port.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v"
+verilog work "../../coregen/fifo_generator_v4_1.v"
+verilog work "../../control_lib/shortfifo.v"
+verilog work "../../control_lib/longfifo.v"
+verilog work "../../sdr_lib/sign_extend.v"
+verilog work "../../sdr_lib/cordic_stage.v"
+verilog work "../../sdr_lib/cic_int_shifter.v"
+verilog work "../../sdr_lib/cic_dec_shifter.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_transmitter.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_sync_flops.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_receiver.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_xecu.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_regf.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_ibuf.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v"
+verilog work "../../opencores/8b10b/encode_8b10b.v"
+verilog work "../../opencores/8b10b/decode_8b10b.v"
+verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v"
+verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v"
+verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v"
+verilog work "../../eth/rtl/verilog/Reg_int.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/Random_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
+verilog work "../../control_lib/ss_rcvr.v"
+verilog work "../../control_lib/cascadefifo2.v"
+verilog work "../../control_lib/CRC16_D16.v"
+verilog work "../../timing/time_sender.v"
+verilog work "../../timing/time_receiver.v"
+verilog work "../../serdes/serdes_tx.v"
+verilog work "../../serdes/serdes_rx.v"
+verilog work "../../serdes/serdes_fc_tx.v"
+verilog work "../../serdes/serdes_fc_rx.v"
+verilog work "../../sdr_lib/round.v"
+verilog work "../../sdr_lib/cordic.v"
+verilog work "../../sdr_lib/cic_interp.v"
+verilog work "../../sdr_lib/cic_decim.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_wb.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_regs.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_debug_if.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_shift.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_clgen.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_edk32.v"
+verilog work "../../eth/rtl/verilog/flow_ctrl_tx.v"
+verilog work "../../eth/rtl/verilog/flow_ctrl_rx.v"
+verilog work "../../eth/rtl/verilog/eth_miim.v"
+verilog work "../../eth/rtl/verilog/RMON.v"
+verilog work "../../eth/rtl/verilog/Phy_int.v"
+verilog work "../../eth/rtl/verilog/MAC_tx.v"
+verilog work "../../eth/rtl/verilog/MAC_rx.v"
+verilog work "../../eth/rtl/verilog/Clk_ctrl.v"
+verilog work "../../control_lib/strobe_gen.v"
+verilog work "../../control_lib/setting_reg.v"
+verilog work "../../control_lib/mux8.v"
+verilog work "../../control_lib/mux4.v"
+verilog work "../../control_lib/icache.v"
+verilog work "../../control_lib/dpram32.v"
+verilog work "../../control_lib/decoder_3_8.v"
+verilog work "../../control_lib/dcache.v"
+verilog work "../../control_lib/buffer_int.v"
+verilog work "../../timing/timer.v"
+verilog work "../../timing/time_sync.v"
+verilog work "../../serdes/serdes.v"
+verilog work "../../sdr_lib/tx_control.v"
+verilog work "../../sdr_lib/rx_control.v"
+verilog work "../../sdr_lib/dsp_core_tx.v"
+verilog work "../../sdr_lib/dsp_core_rx.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_top.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_top.v"
+verilog work "../../opencores/simple_pic/rtl/simple_pic.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v"
+verilog work "../../eth/rtl/verilog/MAC_top.v"
+verilog work "../../eth/mac_txfifo_int.v"
+verilog work "../../eth/mac_rxfifo_int.v"
+verilog work "../../control_lib/wb_readback_mux.v"
+verilog work "../../control_lib/wb_1master.v"
+verilog work "../../control_lib/system_control.v"
+verilog work "../../control_lib/settings_bus.v"
+verilog work "../../control_lib/ram_loader.v"
+verilog work "../../control_lib/ram_harv_cache.v"
+verilog work "../../control_lib/nsgpio.v"
+verilog work "../../control_lib/extram_interface.v"
+verilog work "../../control_lib/buffer_pool.v"
+verilog work "../../control_lib/atr_controller.v"
+verilog work "../u2_basic/u2_basic.v"
+verilog work "u2_fpga_top.v"
diff --git a/usrp2/top/u2_rev1/u2_fpga_top.v b/usrp2/top/u2_rev1/u2_fpga_top.v
new file mode 100644
index 000000000..63798a0c8
--- /dev/null
+++ b/usrp2/top/u2_rev1/u2_fpga_top.v
@@ -0,0 +1,393 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2_fpga_top
+  (
+   // Misc, debug
+   output led1,
+   output led2,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+
+   // Expansion
+   input exp_pps_in_p, // Diff
+   input exp_pps_in_n, // Diff
+   output exp_pps_out_p, // Diff 
+   output exp_pps_out_n, // Diff 
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output reg [7:0] GMII_TXD,
+   output reg GMII_TX_EN,
+   output reg GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+   input PHY_CLK,   // possibly use on-board osc
+
+   // RAM
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output reg [15:0] ser_t,
+   output reg ser_tklsb,
+   output reg ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output cpld_start,  // AA9
+   output cpld_mode,   // U12
+   output cpld_done,   // V12
+   input cpld_din,     // AA14 Now shared with CFG_Din
+   input cpld_clk,     // AB14 serial clock
+
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_oen_a,
+   output adc_pdn_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_oen_b,
+   output adc_pdn_b,
+   
+   // DAC
+   output [15:0] dac_a,
+   output [15:0] dac_b,
+
+   // I2C
+   inout SCL,
+   inout SDA,
+   input SCL_force,
+   input SDA_force,
+
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Clocks
+   input clk_fpga_p,  // Diff
+   input clk_fpga_n,  // Diff
+   input clk_to_mac,
+   input pps_in,
+   
+   // Generic SPI
+   output sclk,
+   output sen_clk,
+   output sen_dac,
+   output sdi,
+   input sdo,
+   
+   // TX DBoard
+   output sen_tx_db,
+   output sclk_tx_db,
+   input sdo_tx_db,
+   output sdi_tx_db,
+
+   output sen_tx_adc,
+   output sclk_tx_adc,
+   input sdo_tx_adc,
+   output sdi_tx_adc,
+
+   output sen_tx_dac,
+   output sclk_tx_dac,
+   output sdi_tx_dac,
+
+   inout [15:0] io_tx,
+
+   // RX DBoard
+   output sen_rx_db,
+   output sclk_rx_db,
+   input sdo_rx_db,
+   output sdi_rx_db,
+
+   output sen_rx_adc,
+   output sclk_rx_adc,
+   input sdo_rx_adc,
+   output sdi_rx_adc,
+
+   output sen_rx_dac,
+   output sclk_rx_dac,
+   output sdi_rx_dac,
+   
+   inout [15:0] io_rx
+   );
+
+   // FPGA-specific pins connections
+   wire 	aux_clk = PHY_CLK;
+   //wire 	cpld_detached = RAM_A[14]; // FIXME  Hacked on with Blue Wire
+   wire 	cpld_detached = SDA_force; // FIXME  Hacked on with Blue Wire
+
+   wire 	clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+
+   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+   defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+   
+   wire 	exp_pps_in;
+   IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+   defparam 	exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+   
+   wire 	exp_pps_out;
+   OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+   defparam 	exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+   reg [5:0] 	clock_ready_d;
+   always @(posedge aux_clk)
+     clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+
+   wire 	dcm_rst = ~&clock_ready_d & |clock_ready_d;
+   wire 	clk_muxed = clock_ready ? clk_fpga : aux_clk;
+
+   wire 	adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+   assign 	adc_oen_a = ~adc_oe_a;
+   assign 	adc_oen_b = ~adc_oe_b;
+   assign 	adc_pdn_a = ~adc_on_a; 	
+   assign 	adc_pdn_b = ~adc_on_b; 	
+
+   // Handle Clocks
+   DCM DCM_INST (.CLKFB(dsp_clk), 
+                 .CLKIN(clk_muxed), 
+                 .DSSEN(0), 
+                 .PSCLK(0), 
+                 .PSEN(0), 
+                 .PSINCDEC(0), 
+                 .RST(dcm_rst), 
+                 .CLKDV(clk_div), 
+                 .CLKFX(), 
+                 .CLKFX180(), 
+                 .CLK0(dcm_out), 
+                 .CLK2X(), 
+                 .CLK2X180(), 
+                 .CLK90(), 
+                 .CLK180(), 
+                 .CLK270(), 
+                 .LOCKED(LOCKED_OUT), 
+                 .PSDONE(), 
+                 .STATUS());
+   defparam DCM_INST.CLK_FEEDBACK = "1X";
+   defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST.CLKFX_DIVIDE = 1;
+   defparam DCM_INST.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST.CLKIN_PERIOD = 10.000;
+   defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST.FACTORY_JF = 16'h8080;
+   defparam DCM_INST.PHASE_SHIFT = 0;
+   defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+   BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+   BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+   // I2C -- Don't use external transistors for open drain, the FPGA implements this
+   IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+   IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+   // LEDs are active low outputs
+   wire 	led1_int, led2_int;
+   assign 	led1 = ~led1_int;
+   assign 	led2 = ~led2_int;
+
+   // SPI
+   wire 	miso, mosi, sclk_int;
+   assign 	{sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+   
+   assign 	miso = (~sen_clk & sdo) | (~sen_dac & sdo) | 
+		(~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+		(~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+   wire 	GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+   wire [7:0] 	GMII_TXD_unreg;
+   wire 	GMII_GTX_CLK_int;
+   
+   always @(posedge GMII_GTX_CLK_int)
+     begin
+	GMII_TX_EN <= GMII_TX_EN_unreg;
+	GMII_TX_ER <= GMII_TX_ER_unreg;
+	GMII_TXD <= GMII_TXD_unreg;
+     end
+
+   OFDDRRSE OFDDRRSE_gmii_inst 
+     (.Q(GMII_GTX_CLK),      // Data output (connect directly to top-level port)
+      .C0(GMII_GTX_CLK_int),    // 0 degree clock input
+      .C1(~GMII_GTX_CLK_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   
+   wire ser_tklsb_unreg, ser_tkmsb_unreg;
+   wire [15:0] ser_t_unreg;
+   wire        ser_tx_clk_int;
+   
+   always @(posedge ser_tx_clk_int)
+     begin
+	ser_tklsb <= ser_tklsb_unreg;
+	ser_tkmsb <= ser_tkmsb_unreg;
+	ser_t <= ser_t_unreg;
+     end
+
+   assign ser_tx_clk = clk_fpga;
+
+   reg [15:0] ser_r_int;
+   reg 	      ser_rklsb_int, ser_rkmsb_int;
+
+   always @(posedge ser_rx_clk)
+     begin
+	ser_r_int <= ser_r;
+	ser_rklsb_int <= ser_rklsb;
+	ser_rkmsb_int <= ser_rkmsb;
+     end
+   
+   /*
+   OFDDRRSE OFDDRRSE_serdes_inst 
+     (.Q(ser_tx_clk),      // Data output (connect directly to top-level port)
+      .C0(ser_tx_clk_int),    // 0 degree clock input
+      .C1(~ser_tx_clk_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   */
+   u2_basic u2_basic(.dsp_clk           (dsp_clk),
+		     .wb_clk            (wb_clk),
+		     .clock_ready       (clock_ready),
+		     .clk_to_mac	(clk_to_mac),
+		     .pps_in		(pps_in),
+		     .led1		(led1_int),
+		     .led2		(led2_int),
+		     .debug		(debug[31:0]),
+		     .debug_clk		(debug_clk[1:0]),
+		     .exp_pps_in	(exp_pps_in),
+		     .exp_pps_out	(exp_pps_out),
+		     .GMII_COL		(GMII_COL),
+		     .GMII_CRS		(GMII_CRS),
+		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
+		     .GMII_TX_EN	(GMII_TX_EN_unreg),
+		     .GMII_TX_ER	(GMII_TX_ER_unreg),
+		     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
+		     .GMII_TX_CLK	(GMII_TX_CLK),
+		     .GMII_RXD		(GMII_RXD[7:0]),
+		     .GMII_RX_CLK	(GMII_RX_CLK),
+		     .GMII_RX_DV	(GMII_RX_DV),
+		     .GMII_RX_ER	(GMII_RX_ER),
+		     .MDIO		(MDIO),
+		     .MDC		(MDC),
+		     .PHY_INTn		(PHY_INTn),
+		     .PHY_RESETn	(PHY_RESETn),
+		     .PHY_CLK		(PHY_CLK),
+		     .ser_enable	(ser_enable),
+		     .ser_prbsen	(ser_prbsen),
+		     .ser_loopen	(ser_loopen),
+		     .ser_rx_en		(ser_rx_en),
+		     .ser_tx_clk	(ser_tx_clk_int),
+		     .ser_t		(ser_t_unreg[15:0]),
+		     .ser_tklsb		(ser_tklsb_unreg),
+		     .ser_tkmsb		(ser_tkmsb_unreg),
+		     .ser_rx_clk	(ser_rx_clk),
+		     .ser_r		(ser_r_int[15:0]),
+		     .ser_rklsb		(ser_rklsb_int),
+		     .ser_rkmsb		(ser_rkmsb_int),
+		     .cpld_start        (cpld_start),
+		     .cpld_mode         (cpld_mode),
+		     .cpld_done         (cpld_done),
+		     .cpld_din          (cpld_din),
+		     .cpld_clk          (cpld_clk),
+		     .cpld_detached     (cpld_detached),
+		     .adc_a		(adc_a[13:0]),
+		     .adc_ovf_a		(adc_ovf_a),
+		     .adc_on_a		(adc_on_a),
+		     .adc_oe_a		(adc_oe_a),
+		     .adc_b		(adc_b[13:0]),
+		     .adc_ovf_b		(adc_ovf_b),
+		     .adc_on_b		(adc_on_b),
+		     .adc_oe_b		(adc_oe_b),
+		     .dac_a		(dac_a[15:0]),
+		     .dac_b		(dac_b[15:0]),
+		     .scl_pad_i		(scl_pad_i),
+		     .scl_pad_o		(scl_pad_o),
+		     .scl_pad_oen_o	(scl_pad_oen_o),
+		     .sda_pad_i		(sda_pad_i),
+		     .sda_pad_o		(sda_pad_o),
+		     .sda_pad_oen_o	(sda_pad_oen_o),
+		     .clk_en		(clk_en[1:0]),
+		     .clk_sel		(clk_sel[1:0]),
+		     .clk_func		(clk_func),
+		     .clk_status	(clk_status),
+		     .sclk		(sclk_int),
+		     .mosi		(mosi),
+		     .miso		(miso),
+		     .sen_clk		(sen_clk),
+		     .sen_dac		(sen_dac),
+		     .sen_tx_db		(sen_tx_db),
+		     .sen_tx_adc	(sen_tx_adc),
+		     .sen_tx_dac	(sen_tx_dac),
+		     .sen_rx_db		(sen_rx_db),
+		     .sen_rx_adc	(sen_rx_adc),
+		     .sen_rx_dac	(sen_rx_dac),
+		     .io_tx		(io_tx[15:0]),
+		     .io_rx		(io_rx[15:0]),
+		     .RAM_D             (RAM_D),
+		     .RAM_A             (RAM_A),
+		     .RAM_CE1n          (RAM_CE1n),
+		     .RAM_CENn          (RAM_CENn),
+		     .RAM_CLK           (RAM_CLK),
+		     .RAM_WEn           (RAM_WEn),
+		     .RAM_OEn           (RAM_OEn),
+		     .RAM_LDn           (RAM_LDn), 
+		     .uart_tx_o         (),
+		     .uart_rx_i         (),
+		     .uart_baud_o       (),
+		     .sim_mode          (1'b0),
+		     .clock_divider     (2)
+		     );
+   
+endmodule // u2_fpga_top
diff --git a/usrp2/top/u2_rev2/.gitignore b/usrp2/top/u2_rev2/.gitignore
new file mode 100644
index 000000000..432f8fd58
--- /dev/null
+++ b/usrp2/top/u2_rev2/.gitignore
@@ -0,0 +1,57 @@
+/*.ptwx
+/*.xrpt
+/*.zip
+/*_xdb
+/templates
+/netgen
+/_ngo
+/_xmsgs
+/_pace.ucf
+/*.cmd
+/*.ibs
+/*.lfp
+/*.mfp
+/*.bit
+/*.bin
+/*.stx
+/*.par
+/*.unroutes
+/*.ntrc_log
+/*.ngr
+/*.mrp
+/*.html
+/*.lso
+/*.twr
+/*.bld
+/*.ncd
+/*.txt
+/*.cmd_log
+/*.drc
+/*.map
+/*.twr
+/*.xml
+/*.syr
+/*.ngm
+/*.xst
+/*.csv
+/*.html
+/*.lock
+/*.ncd
+/*.twx
+/*.ise_ISE_Backup
+/*.xml
+/*.ut
+/*.xpi
+/*.ngd
+/*.ncd
+/*.pad
+/*.bgn
+/*.ngc
+/*.pcf
+/*.ngd
+/xst
+/*.log
+/*.rpt
+/*.cel
+/*.restore
+/build
diff --git a/usrp2/top/u2_rev2/Makefile b/usrp2/top/u2_rev2/Makefile
new file mode 100644
index 000000000..275c24b02
--- /dev/null
+++ b/usrp2/top/u2_rev2/Makefile
@@ -0,0 +1,248 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u2_rev2
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family Spartan3 \
+device xc3s2000 \
+package fg456 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/buffer_int.v \
+control_lib/buffer_pool.v \
+control_lib/cascadefifo2.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/fifo_2clock.v \
+control_lib/fifo_2clock_casc.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/longfifo.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+eth/mac_rxfifo_int.v \
+eth/mac_txfifo_int.v \
+eth/rtl/verilog/Clk_ctrl.v \
+eth/rtl/verilog/MAC_rx.v \
+eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
+eth/rtl/verilog/MAC_rx/CRC_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
+eth/rtl/verilog/MAC_top.v \
+eth/rtl/verilog/MAC_tx.v \
+eth/rtl/verilog/MAC_tx/CRC_gen.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
+eth/rtl/verilog/MAC_tx/Random_gen.v \
+eth/rtl/verilog/Phy_int.v \
+eth/rtl/verilog/RMON.v \
+eth/rtl/verilog/RMON/RMON_addr_gen.v \
+eth/rtl/verilog/RMON/RMON_ctrl.v \
+eth/rtl/verilog/Reg_int.v \
+eth/rtl/verilog/eth_miim.v \
+eth/rtl/verilog/flow_ctrl_rx.v \
+eth/rtl/verilog/flow_ctrl_tx.v \
+eth/rtl/verilog/miim/eth_clockgen.v \
+eth/rtl/verilog/miim/eth_outputcontrol.v \
+eth/rtl/verilog/miim/eth_shiftreg.v \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u2_rev2/u2_rev2.ucf \
+top/u2_rev2/u2_rev2.v 
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High 
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+	@echo make proj, check, synth, bin, or clean
+
+proj:
+	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
+
+check:
+	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
+
+synth:
+	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
+
+bin:
+	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+
diff --git a/usrp2/top/u2_rev2/u2_rev2.ucf b/usrp2/top/u2_rev2/u2_rev2.ucf
new file mode 100644
index 000000000..e18dc6f17
--- /dev/null
+++ b/usrp2/top/u2_rev2/u2_rev2.ucf
@@ -0,0 +1,337 @@
+NET "leds[0]"  LOC = "F7"  ; 
+NET "leds[1]"  LOC = "E5"  ; 
+NET "leds[2]"  LOC = "B7"  ; 
+NET "leds[3]"  LOC = "C11"  ; 
+NET "leds[4]"  LOC = "AB19"  ;
+NET "debug[0]"  LOC = "N5"  ;
+NET "debug[1]"  LOC = "N6"  ;
+NET "debug[2]"  LOC = "P1"  ;
+NET "debug[3]"  LOC = "P2"  ;
+NET "debug[4]"  LOC = "P4"  ;
+NET "debug[5]"  LOC = "P5"  ;
+NET "debug[6]"  LOC = "R1"  ;
+NET "debug[7]"  LOC = "R2"  ;
+NET "debug[8]"  LOC = "P6"  ;
+NET "debug[9]"  LOC = "R5"  ;
+NET "debug[10]"  LOC = "R4"  ;
+NET "debug[11]"  LOC = "T3"  ;
+NET "debug[12]"  LOC = "U3"  ;
+NET "debug[13]"  LOC = "M2"  ;
+NET "debug[14]"  LOC = "M3"  ;
+NET "debug[15]"  LOC = "M4"  ;
+NET "debug[16]"  LOC = "M5"  ;
+NET "debug[17]"  LOC = "M6"  ;
+NET "debug[18]"  LOC = "N1"  ;
+NET "debug[19]"  LOC = "N2"  ;
+NET "debug[20]"  LOC = "N3"  ;
+NET "debug[21]"  LOC = "T1"  ;
+NET "debug[22]"  LOC = "T2"  ;
+NET "debug[23]"  LOC = "U2"  ;
+NET "debug[24]"  LOC = "T4"  ;
+NET "debug[25]"  LOC = "U4"  ;
+NET "debug[26]"  LOC = "T5"  ;
+NET "debug[27]"  LOC = "T6"  ;
+NET "debug[28]"  LOC = "U5"  ;
+NET "debug[29]"  LOC = "V5"  ;
+NET "debug[30]"  LOC = "W2"  ;
+NET "debug[31]"  LOC = "W3"  ;
+NET "debug_clk[0]"  LOC = "N4"  ;
+NET "debug_clk[1]"  LOC = "M1"  ;
+NET "uart_tx_o"  LOC = "C7"  ;
+NET "uart_rx_i"  LOC = "A3"  ;
+NET "exp_pps_in_p"  LOC = "V3"  ; 
+NET "exp_pps_in_n"  LOC = "V4"  ; 
+NET "exp_pps_out_p"  LOC = "V1"  ; 
+NET "exp_pps_out_n"  LOC = "V2"  ; 
+NET "GMII_COL"  LOC = "U16"  ; 
+NET "GMII_CRS"  LOC = "U17"  ; 
+NET "GMII_TXD[0]"  LOC = "W14"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[1]"  LOC = "AA20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[2]"  LOC = "AB20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[3]"  LOC = "Y18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[4]"  LOC = "AA18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[5]"  LOC = "AB18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[6]"  LOC = "V17"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[7]"  LOC = "W17"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TX_EN"  LOC = "Y17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_TX_ER"  LOC = "V16" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_GTX_CLK"  LOC = "AA17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_TX_CLK"  LOC = "W13"  ; 
+NET "GMII_RXD[0]"  LOC = "AA15"  ;
+NET "GMII_RXD[1]"  LOC = "AB15"  ;
+NET "GMII_RXD[2]"  LOC = "U14"  ;
+NET "GMII_RXD[3]"  LOC = "V14"  ;
+NET "GMII_RXD[4]"  LOC = "U13"  ;
+NET "GMII_RXD[5]"  LOC = "V13"  ;
+NET "GMII_RXD[6]"  LOC = "Y13"  ;
+NET "GMII_RXD[7]"  LOC = "AA13"  ;
+NET "GMII_RX_CLK"  LOC = "W16"  ; 
+NET "GMII_RX_DV"  LOC = "AB16"  ; 
+NET "GMII_RX_ER"  LOC = "AA16"  ; 
+NET "MDIO"  LOC = "Y16" |PULLUP ; 
+NET "MDC"  LOC = "V18"  ; 
+NET "PHY_INTn"  LOC = "AB13"  ; 
+NET "PHY_RESETn"  LOC = "AA19"  ; 
+NET "PHY_CLK"  LOC = "V15"  ; 
+NET "RAM_D[0]"  LOC = "N20"  ;
+NET "RAM_D[1]"  LOC = "N21"  ;
+NET "RAM_D[2]"  LOC = "N22"  ;
+NET "RAM_D[3]"  LOC = "M17"  ;
+NET "RAM_D[4]"  LOC = "M18"  ;
+NET "RAM_D[5]"  LOC = "M19"  ;
+NET "RAM_D[6]"  LOC = "M20"  ;
+NET "RAM_D[7]"  LOC = "M21"  ;
+NET "RAM_D[8]"  LOC = "M22"  ;
+NET "RAM_D[9]"  LOC = "Y22"  ;
+NET "RAM_D[10]"  LOC = "Y21"  ;
+NET "RAM_D[11]"  LOC = "Y20"  ;
+NET "RAM_D[12]"  LOC = "Y19"  ;
+NET "RAM_D[13]"  LOC = "W22"  ;
+NET "RAM_D[14]"  LOC = "W21"  ;
+NET "RAM_D[15]"  LOC = "W20"  ;
+NET "RAM_D[16]"  LOC = "W19"  ;
+NET "RAM_D[17]"  LOC = "V22"  ;
+NET "RAM_A[0]"  LOC = "U21"  ;
+NET "RAM_A[1]"  LOC = "T19"  ;
+NET "RAM_A[2]"  LOC = "V21"  ;
+NET "RAM_A[3]"  LOC = "V20"  ;
+NET "RAM_A[4]"  LOC = "T20"  ;
+NET "RAM_A[5]"  LOC = "T21"  ;
+NET "RAM_A[6]"  LOC = "T22"  ;
+NET "RAM_A[7]"  LOC = "T18"  ;
+NET "RAM_A[8]"  LOC = "R18"  ;
+NET "RAM_A[9]"  LOC = "P19"  ;
+NET "RAM_A[10]"  LOC = "P21"  ;
+NET "RAM_A[11]"  LOC = "P22"  ;
+NET "RAM_A[12]"  LOC = "N19"  ;
+NET "RAM_A[13]"  LOC = "N17"  ;
+NET "RAM_A[14]"  LOC = "N18"  ;
+NET "RAM_A[15]"  LOC = "T17"  ;
+NET "RAM_A[16]"  LOC = "U19"  ;
+NET "RAM_A[17]"  LOC = "U18"  ;
+NET "RAM_A[18]"  LOC = "V19"  ;
+NET "RAM_CE1n"  LOC = "U20"  ; 
+NET "RAM_CENn"  LOC = "P18"  ; 
+NET "RAM_CLK"  LOC = "P17"  ; 
+NET "RAM_WEn"  LOC = "R22"  ; 
+NET "RAM_OEn"  LOC = "R21"  ; 
+NET "RAM_LDn"  LOC = "R19"  ; 
+NET "ser_enable"  LOC = "W11"  ; 
+NET "ser_prbsen"  LOC = "AA3"  ; 
+NET "ser_loopen"  LOC = "Y4"  ; 
+NET "ser_rx_en"  LOC = "AB9"  ; 
+NET "ser_tx_clk"  LOC = "U7" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_t[0]"  LOC = "V7"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[1]"  LOC = "V10"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[2]"  LOC = "AB4"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[3]"  LOC = "AA4"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[4]"  LOC = "Y5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[5]"  LOC = "W5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[6]"  LOC = "AB5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[7]"  LOC = "AA5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[8]"  LOC = "W6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[9]"  LOC = "V6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[10]"  LOC = "AA6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[11]"  LOC = "Y6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[12]"  LOC = "W8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[13]"  LOC = "V8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[14]"  LOC = "AB8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[15]"  LOC = "AA8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_tklsb"  LOC = "U10" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_tkmsb"  LOC = "U11" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_rx_clk"  LOC = "AA11"  ; 
+NET "ser_r[0]"  LOC = "AB10"  ;
+NET "ser_r[1]"  LOC = "AA10"  ;
+NET "ser_r[2]"  LOC = "U9"  ;
+NET "ser_r[3]"  LOC = "U6"  ;
+NET "ser_r[4]"  LOC = "AB11"  ;
+NET "ser_r[5]"  LOC = "Y7"  ;
+NET "ser_r[6]"  LOC = "W7"  ;
+NET "ser_r[7]"  LOC = "AB7"  ;
+NET "ser_r[8]"  LOC = "AA7"  ;
+NET "ser_r[9]"  LOC = "W9"  ;
+NET "ser_r[10]"  LOC = "W10"  ;
+NET "ser_r[11]"  LOC = "Y1"  ;
+NET "ser_r[12]"  LOC = "Y3"  ;
+NET "ser_r[13]"  LOC = "Y2"  ;
+NET "ser_r[14]"  LOC = "W4"  ;
+NET "ser_r[15]"  LOC = "W1"  ;
+NET "ser_rklsb"  LOC = "V9"  ;
+NET "ser_rkmsb"  LOC = "Y10"  ; 
+NET "cpld_start"  LOC = "AA9"  ; 
+NET "cpld_mode"  LOC = "U12"  ; 
+NET "cpld_done"  LOC = "V12"  ; 
+NET "cpld_din"  LOC = "AA14"  ; 
+NET "cpld_clk"  LOC = "AB14"  ; 
+NET "cpld_detached"  LOC = "V11"  ;
+NET "cpld_init_b"  LOC = "W12"  ;
+NET "cpld_misc"  LOC = "Y12"  ;
+NET "adc_a[0]"  LOC = "A14" | IOBDELAY= "NONE" ;
+NET "adc_a[1]"  LOC = "B14" | IOBDELAY= "NONE" ;
+NET "adc_a[2]"  LOC = "C13" | IOBDELAY= "NONE" ;
+NET "adc_a[3]"  LOC = "D13" | IOBDELAY= "NONE" ;
+NET "adc_a[4]"  LOC = "A13" | IOBDELAY= "NONE" ;
+NET "adc_a[5]"  LOC = "B13" | IOBDELAY= "NONE" ;
+NET "adc_a[6]"  LOC = "E12" | IOBDELAY= "NONE" ;
+NET "adc_a[7]"  LOC = "C22" | IOBDELAY= "NONE" ;
+NET "adc_a[8]"  LOC = "C20" | IOBDELAY= "NONE" ;
+NET "adc_a[9]"  LOC = "C21" | IOBDELAY= "NONE" ;
+NET "adc_a[10]"  LOC = "D20" | IOBDELAY= "NONE" ;
+NET "adc_a[11]"  LOC = "D19" | IOBDELAY= "NONE" ;
+NET "adc_a[12]"  LOC = "D21" | IOBDELAY= "NONE" ;
+NET "adc_a[13]"  LOC = "E18" | IOBDELAY= "NONE" ;
+NET "adc_ovf_a"  LOC = "F18"  ; 
+NET "adc_oen_a"  LOC = "E19"  ; 
+NET "adc_pdn_a"  LOC = "E20"  ; 
+NET "adc_b[0]"  LOC = "A12" | IOBDELAY= "NONE";
+NET "adc_b[1]"  LOC = "E16" | IOBDELAY= "NONE" ;
+NET "adc_b[2]"  LOC = "F12" | IOBDELAY= "NONE" ;
+NET "adc_b[3]"  LOC = "F13" | IOBDELAY= "NONE" ;
+NET "adc_b[4]"  LOC = "F16" | IOBDELAY= "NONE" ;
+NET "adc_b[5]"  LOC = "F17" | IOBDELAY= "NONE" ;
+NET "adc_b[6]"  LOC = "C19" | IOBDELAY= "NONE" ;
+NET "adc_b[7]"  LOC = "B20" | IOBDELAY= "NONE" ;
+NET "adc_b[8]"  LOC = "B19" | IOBDELAY= "NONE" ;
+NET "adc_b[9]"  LOC = "C18" | IOBDELAY= "NONE" ;
+NET "adc_b[10]"  LOC = "D18" | IOBDELAY= "NONE" ;
+NET "adc_b[11]"  LOC = "B18" | IOBDELAY= "NONE" ;
+NET "adc_b[12]"  LOC = "D17" | IOBDELAY= "NONE" ;
+NET "adc_b[13]"  LOC = "E17" | IOBDELAY= "NONE" ;
+NET "adc_ovf_b"  LOC = "B17"  ; 
+NET "adc_oen_b"  LOC = "C17"  ; 
+NET "adc_pdn_b"  LOC = "D15"  ; 
+NET "dac_a[0]"  LOC = "A5"  ;
+NET "dac_a[1]"  LOC = "B5"  ;
+NET "dac_a[2]"  LOC = "C5"  ;
+NET "dac_a[3]"  LOC = "D5"  ;
+NET "dac_a[4]"  LOC = "A4"  ;
+NET "dac_a[5]"  LOC = "B4"  ;
+NET "dac_a[6]"  LOC = "F6"  ;
+NET "dac_a[7]"  LOC = "D10"  ;
+NET "dac_a[8]"  LOC = "D9"  ;
+NET "dac_a[9]"  LOC = "A10"  ;
+NET "dac_a[10]"  LOC = "L2"  ;
+NET "dac_a[11]"  LOC = "L4"  ;
+NET "dac_a[12]"  LOC = "L3"  ;
+NET "dac_a[13]"  LOC = "L6"  ;
+NET "dac_a[14]"  LOC = "L5"  ;
+NET "dac_a[15]"  LOC = "K2"  ;
+NET "dac_b[0]"  LOC = "D11"  ;
+NET "dac_b[1]"  LOC = "E11"  ;
+NET "dac_b[2]"  LOC = "F11"  ;
+NET "dac_b[3]"  LOC = "B10"  ;
+NET "dac_b[4]"  LOC = "C10"  ;
+NET "dac_b[5]"  LOC = "E10"  ;
+NET "dac_b[6]"  LOC = "F10"  ;
+NET "dac_b[7]"  LOC = "A9"  ;
+NET "dac_b[8]"  LOC = "B9"  ;
+NET "dac_b[9]"  LOC = "E9"  ;
+NET "dac_b[10]"  LOC = "F9"  ;
+NET "dac_b[11]"  LOC = "A8"  ;
+NET "dac_b[12]"  LOC = "B8"  ;
+NET "dac_b[13]"  LOC = "D7"  ;
+NET "dac_b[14]"  LOC = "E7"  ;
+NET "dac_b[15]"  LOC = "B6"  ;
+NET "dac_lock"  LOC = "D6"  ;
+NET "SCL"  LOC = "A7"  ; 
+NET "SDA"  LOC = "D8"  ; 
+NET "clk_en[0]"  LOC = "C4"  ;
+NET "clk_en[1]"  LOC = "D1"  ;
+NET "clk_sel[0]"  LOC = "C3"  ;
+NET "clk_sel[1]"  LOC = "C2"  ;
+NET "clk_func"  LOC = "C12"  ; 
+NET "clk_status"  LOC = "B12"  ; 
+NET "clk_fpga_p"  LOC = "A11"  ; 
+NET "clk_fpga_n"  LOC = "B11"  ; 
+NET "clk_to_mac"  LOC = "AB12"  ; 
+NET "pps_in"  LOC = "Y11"  ; 
+NET "sclk"  LOC = "K5"  ; 
+NET "sen_clk"  LOC = "K6"  ; 
+NET "sen_dac"  LOC = "L1"  ; 
+NET "sdi"  LOC = "J1"  ; 
+NET "sdo"  LOC = "J2"  ; 
+NET "sen_tx_db"  LOC = "C1"  ; 
+NET "sclk_tx_db"  LOC = "D3"  ; 
+NET "sdo_tx_db"  LOC = "G3"  ; 
+NET "sdi_tx_db"  LOC = "G4"  ; 
+NET "sen_tx_adc"  LOC = "G2"  ; 
+NET "sclk_tx_adc"  LOC = "H1"  ; 
+NET "sdo_tx_adc"  LOC = "H2"  ; 
+NET "sdi_tx_adc"  LOC = "J4"  ; 
+NET "sen_tx_dac"  LOC = "H4"  ; 
+NET "sclk_tx_dac"  LOC = "J5"  ; 
+NET "sdi_tx_dac"  LOC = "J6"  ; 
+NET "io_tx[0]"  LOC = "K4"  ;
+NET "io_tx[1]"  LOC = "K3"  ;
+NET "io_tx[2]"  LOC = "G1"  ;
+NET "io_tx[3]"  LOC = "G5"  ;
+NET "io_tx[4]"  LOC = "H5"  ;
+NET "io_tx[5]"  LOC = "F3"  ;
+NET "io_tx[6]"  LOC = "F2"  ;
+NET "io_tx[7]"  LOC = "F5"  ;
+NET "io_tx[8]"  LOC = "G6"  ;
+NET "io_tx[9]"  LOC = "E2"  ;
+NET "io_tx[10]"  LOC = "E1"  ;
+NET "io_tx[11]"  LOC = "E3"  ;
+NET "io_tx[12]"  LOC = "F4"  ;
+NET "io_tx[13]"  LOC = "D2"  ;
+NET "io_tx[14]"  LOC = "D4"  ;
+NET "io_tx[15]"  LOC = "E4"  ;
+NET "sen_rx_db"  LOC = "D22"  ; 
+NET "sclk_rx_db"  LOC = "F19"  ; 
+NET "sdo_rx_db"  LOC = "G20"  ; 
+NET "sdi_rx_db"  LOC = "H19"  ; 
+NET "sen_rx_adc"  LOC = "H18"  ; 
+NET "sclk_rx_adc"  LOC = "J17"  ; 
+NET "sdo_rx_adc"  LOC = "H21"  ; 
+NET "sdi_rx_adc"  LOC = "H22"  ; 
+NET "sen_rx_dac"  LOC = "J18"  ; 
+NET "sclk_rx_dac"  LOC = "J19"  ; 
+NET "sdi_rx_dac"  LOC = "J21"  ; 
+NET "io_rx[0]"  LOC = "L21"  ;
+NET "io_rx[1]"  LOC = "L20"  ;
+NET "io_rx[2]"  LOC = "L19"  ;
+NET "io_rx[3]"  LOC = "L18"  ;
+NET "io_rx[4]"  LOC = "L17"  ;
+NET "io_rx[5]"  LOC = "K22"  ;
+NET "io_rx[6]"  LOC = "K21"  ;
+NET "io_rx[7]"  LOC = "K20"  ;
+NET "io_rx[8]"  LOC = "G22"  ;
+NET "io_rx[9]"  LOC = "G21"  ;
+NET "io_rx[10]"  LOC = "F21"  ;
+NET "io_rx[11]"  LOC = "F20"  ;
+NET "io_rx[12]"  LOC = "G19"  ;
+NET "io_rx[13]"  LOC = "G18"  ;
+NET "io_rx[14]"  LOC = "G17"  ;
+NET "io_rx[15]"  LOC = "E22"  ;
+
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+
+#NET "dsp_clk" TNM_NET = "dsp_clk";
+#TIMESPEC "TS_dsp_clk" = PERIOD "dsp_clk" 10 ns HIGH 50 %;
+
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
+
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+
+#NET "wb_clk" TNM_NET = "wb_clk";
+#TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" 20 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; 
+NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
+
+#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
+#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
+#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+
+#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
diff --git a/usrp2/top/u2_rev2/u2_rev2.v b/usrp2/top/u2_rev2/u2_rev2.v
new file mode 100644
index 000000000..517285e52
--- /dev/null
+++ b/usrp2/top/u2_rev2/u2_rev2.v
@@ -0,0 +1,417 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2_rev2
+  (
+   // Misc, debug
+   output [4:0] leds,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+   output uart_tx_o,
+   input uart_rx_i,
+   
+   // Expansion
+   input exp_pps_in_p, // Diff
+   input exp_pps_in_n, // Diff
+   output exp_pps_out_p, // Diff 
+   output exp_pps_out_n, // Diff 
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output reg [7:0] GMII_TXD,
+   output reg GMII_TX_EN,
+   output reg GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+   input PHY_CLK,   // possibly use on-board osc
+
+   // RAM
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output reg [15:0] ser_t,
+   output reg ser_tklsb,
+   output reg ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output cpld_start,  // AA9
+   output cpld_mode,   // U12
+   output cpld_done,   // V12
+   input cpld_din,     // AA14 Now shared with CFG_Din
+   input cpld_clk,     // AB14 serial clock
+   input cpld_detached,// V11 unused
+   output cpld_init_b,  // W12 unused dual purpose
+   output cpld_misc,  // Y12 
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_oen_a,
+   output adc_pdn_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_oen_b,
+   output adc_pdn_b,
+   
+   // DAC
+   output reg [15:0] dac_a,
+   output reg [15:0] dac_b,
+   input dac_lock,     // unused for now
+   
+   // I2C
+   inout SCL,
+   inout SDA,
+
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Clocks
+   input clk_fpga_p,  // Diff
+   input clk_fpga_n,  // Diff
+   input clk_to_mac,
+   input pps_in,
+   
+   // Generic SPI
+   output sclk,
+   output sen_clk,
+   output sen_dac,
+   output sdi,
+   input sdo,
+   
+   // TX DBoard
+   output sen_tx_db,
+   output sclk_tx_db,
+   input sdo_tx_db,
+   output sdi_tx_db,
+
+   output sen_tx_adc,
+   output sclk_tx_adc,
+   input sdo_tx_adc,
+   output sdi_tx_adc,
+
+   output sen_tx_dac,
+   output sclk_tx_dac,
+   output sdi_tx_dac,
+
+   inout [15:0] io_tx,
+
+   // RX DBoard
+   output sen_rx_db,
+   output sclk_rx_db,
+   input sdo_rx_db,
+   output sdi_rx_db,
+
+   output sen_rx_adc,
+   output sclk_rx_adc,
+   input sdo_rx_adc,
+   output sdi_rx_adc,
+
+   output sen_rx_dac,
+   output sclk_rx_dac,
+   output sdi_rx_dac,
+   
+   inout [15:0] io_rx   
+   );
+
+   assign 	cpld_init_b = 0;
+   // FPGA-specific pins connections
+   wire 	clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+   wire 	clk90, clk180, clk270;
+
+   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+   defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+   
+   wire 	exp_pps_in;
+   IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+   defparam 	exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+   
+   wire 	exp_pps_out;
+   OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+   defparam 	exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+   reg [5:0] 	clock_ready_d;
+   always @(posedge clk_fpga)
+     clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+   wire 	dcm_rst = ~&clock_ready_d & |clock_ready_d;
+   
+   wire 	adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+   assign 	adc_oen_a = ~adc_oe_a;
+   assign 	adc_oen_b = ~adc_oe_b;
+   assign 	adc_pdn_a = ~adc_on_a; 	
+   assign 	adc_pdn_b = ~adc_on_b; 	
+
+   reg [13:0] 	 adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
+   reg 		 adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
+
+   always @(posedge dsp_clk)
+     begin
+	adc_a_reg1 <= adc_a;
+	adc_b_reg1 <= adc_b;
+	adc_ovf_a_reg1 <= adc_ovf_a;
+	adc_ovf_b_reg1 <= adc_ovf_b;
+     end
+   
+   always @(posedge dsp_clk)
+     begin
+	adc_a_reg2 <= adc_a_reg1;
+	adc_b_reg2 <= adc_b_reg1;
+	adc_ovf_a_reg2 <= adc_ovf_a_reg1;
+	adc_ovf_b_reg2 <= adc_ovf_b_reg1;
+     end // always @ (posedge dsp_clk)
+
+   // Handle Clocks
+   DCM DCM_INST (.CLKFB(dsp_clk), 
+                 .CLKIN(clk_fpga), 
+                 .DSSEN(0), 
+                 .PSCLK(0), 
+                 .PSEN(0), 
+                 .PSINCDEC(0), 
+                 .RST(dcm_rst), 
+                 .CLKDV(clk_div), 
+                 .CLKFX(), 
+                 .CLKFX180(), 
+                 .CLK0(dcm_out), 
+                 .CLK2X(), 
+                 .CLK2X180(), 
+                 .CLK90(clk90), 
+                 .CLK180(clk180), 
+                 .CLK270(clk270), 
+                 .LOCKED(LOCKED_OUT), 
+                 .PSDONE(), 
+                 .STATUS());
+   defparam DCM_INST.CLK_FEEDBACK = "1X";
+   defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST.CLKFX_DIVIDE = 1;
+   defparam DCM_INST.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST.CLKIN_PERIOD = 10.000;
+   defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST.FACTORY_JF = 16'h8080;
+   defparam DCM_INST.PHASE_SHIFT = 0;
+   defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+   BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+   BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+   // I2C -- Don't use external transistors for open drain, the FPGA implements this
+   IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+   IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+   // LEDs are active low outputs
+   wire [4:0] leds_int;
+   assign     leds = 5'b01111 ^ leds_int;  // all except eth are active-low
+   
+   // SPI
+   wire 	miso, mosi, sclk_int;
+   assign 	{sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+   
+   assign 	miso = (~sen_clk & sdo) | (~sen_dac & sdo) | 
+		(~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+		(~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+   wire 	GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+   wire [7:0] 	GMII_TXD_unreg;
+   wire 	GMII_GTX_CLK_int;
+   
+   always @(posedge GMII_GTX_CLK_int)
+     begin
+	GMII_TX_EN <= GMII_TX_EN_unreg;
+	GMII_TX_ER <= GMII_TX_ER_unreg;
+	GMII_TXD <= GMII_TXD_unreg;
+     end
+
+   OFDDRRSE OFDDRRSE_gmii_inst 
+     (.Q(GMII_GTX_CLK),      // Data output (connect directly to top-level port)
+      .C0(GMII_GTX_CLK_int),    // 0 degree clock input
+      .C1(~GMII_GTX_CLK_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   
+   wire ser_tklsb_unreg, ser_tkmsb_unreg;
+   wire [15:0] ser_t_unreg;
+   wire        ser_tx_clk_int;
+   
+   always @(posedge ser_tx_clk_int)
+     begin
+	ser_tklsb <= ser_tklsb_unreg;
+	ser_tkmsb <= ser_tkmsb_unreg;
+	ser_t <= ser_t_unreg;
+     end
+
+   assign ser_tx_clk = clk_fpga;
+
+   reg [15:0] ser_r_int;
+   reg 	      ser_rklsb_int, ser_rkmsb_int;
+
+   always @(posedge ser_rx_clk)
+     begin
+	ser_r_int <= ser_r;
+	ser_rklsb_int <= ser_rklsb;
+	ser_rkmsb_int <= ser_rkmsb;
+     end
+
+   wire [15:0] dac_a_int, dac_b_int;
+   always @(negedge dsp_clk) dac_a <= dac_a_int;
+   always @(negedge dsp_clk) dac_b <= dac_b_int;
+
+   /*
+   OFDDRRSE OFDDRRSE_serdes_inst 
+     (.Q(ser_tx_clk),      // Data output (connect directly to top-level port)
+      .C0(ser_tx_clk_int),    // 0 degree clock input
+      .C1(~ser_tx_clk_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   */
+   u2_core #(.RAM_SIZE(32768))
+	u2_core(.dsp_clk           (dsp_clk),
+		     .wb_clk            (wb_clk),
+		     .clock_ready       (clock_ready),
+		     .clk_to_mac	(clk_to_mac),
+		     .pps_in		(pps_in),
+		     .leds		(leds_int),
+		     .debug		(debug[31:0]),
+		     .debug_clk		(debug_clk[1:0]),
+		     .exp_pps_in	(exp_pps_in),
+		     .exp_pps_out	(exp_pps_out),
+		     .GMII_COL		(GMII_COL),
+		     .GMII_CRS		(GMII_CRS),
+		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
+		     .GMII_TX_EN	(GMII_TX_EN_unreg),
+		     .GMII_TX_ER	(GMII_TX_ER_unreg),
+		     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
+		     .GMII_TX_CLK	(GMII_TX_CLK),
+		     .GMII_RXD		(GMII_RXD[7:0]),
+		     .GMII_RX_CLK	(GMII_RX_CLK),
+		     .GMII_RX_DV	(GMII_RX_DV),
+		     .GMII_RX_ER	(GMII_RX_ER),
+		     .MDIO		(MDIO),
+		     .MDC		(MDC),
+		     .PHY_INTn		(PHY_INTn),
+		     .PHY_RESETn	(PHY_RESETn),
+		     .ser_enable	(ser_enable),
+		     .ser_prbsen	(ser_prbsen),
+		     .ser_loopen	(ser_loopen),
+		     .ser_rx_en		(ser_rx_en),
+		     .ser_tx_clk	(ser_tx_clk_int),
+		     .ser_t		(ser_t_unreg[15:0]),
+		     .ser_tklsb		(ser_tklsb_unreg),
+		     .ser_tkmsb		(ser_tkmsb_unreg),
+		     .ser_rx_clk	(ser_rx_clk),
+		     .ser_r		(ser_r_int[15:0]),
+		     .ser_rklsb		(ser_rklsb_int),
+		     .ser_rkmsb		(ser_rkmsb_int),
+		     .cpld_start        (cpld_start),
+		     .cpld_mode         (cpld_mode),
+		     .cpld_done         (cpld_done),
+		     .cpld_din          (cpld_din),
+		     .cpld_clk          (cpld_clk),
+		     .cpld_detached     (cpld_detached),
+		     .cpld_misc         (cpld_misc),
+		     .cpld_init_b       (cpld_init_b),
+		     .por               (~POR),
+		     .config_success    (config_success),
+		     .adc_a		(adc_a_reg2),
+		     .adc_ovf_a		(adc_ovf_a_reg2),
+		     .adc_on_a		(adc_on_a),
+		     .adc_oe_a		(adc_oe_a),
+		     .adc_b		(adc_b_reg2),
+		     .adc_ovf_b		(adc_ovf_b_reg2),
+		     .adc_on_b		(adc_on_b),
+		     .adc_oe_b		(adc_oe_b),
+		     .dac_a		(dac_a_int),
+		     .dac_b		(dac_b_int),
+		     .scl_pad_i		(scl_pad_i),
+		     .scl_pad_o		(scl_pad_o),
+		     .scl_pad_oen_o	(scl_pad_oen_o),
+		     .sda_pad_i		(sda_pad_i),
+		     .sda_pad_o		(sda_pad_o),
+		     .sda_pad_oen_o	(sda_pad_oen_o),
+		     .clk_en		(clk_en[1:0]),
+		     .clk_sel		(clk_sel[1:0]),
+		     .clk_func		(clk_func),
+		     .clk_status	(clk_status),
+		     .sclk		(sclk_int),
+		     .mosi		(mosi),
+		     .miso		(miso),
+		     .sen_clk		(sen_clk),
+		     .sen_dac		(sen_dac),
+		     .sen_tx_db		(sen_tx_db),
+		     .sen_tx_adc	(sen_tx_adc),
+		     .sen_tx_dac	(sen_tx_dac),
+		     .sen_rx_db		(sen_rx_db),
+		     .sen_rx_adc	(sen_rx_adc),
+		     .sen_rx_dac	(sen_rx_dac),
+		     .io_tx		(io_tx[15:0]),
+		     .io_rx		(io_rx[15:0]),
+		     .RAM_D             (RAM_D),
+		     .RAM_A             (RAM_A),
+		     .RAM_CE1n          (RAM_CE1n),
+		     .RAM_CENn          (RAM_CENn),
+		     .RAM_CLK           (RAM_CLK),
+		     .RAM_WEn           (RAM_WEn),
+		     .RAM_OEn           (RAM_OEn),
+		     .RAM_LDn           (RAM_LDn), 
+		     .uart_tx_o         (uart_tx_o),
+		     .uart_rx_i         (uart_rx_i),
+		     .uart_baud_o       (),
+		     .sim_mode          (1'b0),
+		     .clock_divider     (2)
+		     );
+   
+endmodule // u2_rev2
diff --git a/usrp2/top/u2_rev3/.gitignore b/usrp2/top/u2_rev3/.gitignore
new file mode 100644
index 000000000..432f8fd58
--- /dev/null
+++ b/usrp2/top/u2_rev3/.gitignore
@@ -0,0 +1,57 @@
+/*.ptwx
+/*.xrpt
+/*.zip
+/*_xdb
+/templates
+/netgen
+/_ngo
+/_xmsgs
+/_pace.ucf
+/*.cmd
+/*.ibs
+/*.lfp
+/*.mfp
+/*.bit
+/*.bin
+/*.stx
+/*.par
+/*.unroutes
+/*.ntrc_log
+/*.ngr
+/*.mrp
+/*.html
+/*.lso
+/*.twr
+/*.bld
+/*.ncd
+/*.txt
+/*.cmd_log
+/*.drc
+/*.map
+/*.twr
+/*.xml
+/*.syr
+/*.ngm
+/*.xst
+/*.csv
+/*.html
+/*.lock
+/*.ncd
+/*.twx
+/*.ise_ISE_Backup
+/*.xml
+/*.ut
+/*.xpi
+/*.ngd
+/*.ncd
+/*.pad
+/*.bgn
+/*.ngc
+/*.pcf
+/*.ngd
+/xst
+/*.log
+/*.rpt
+/*.cel
+/*.restore
+/build
diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile
new file mode 100644
index 000000000..d27469f47
--- /dev/null
+++ b/usrp2/top/u2_rev3/Makefile
@@ -0,0 +1,263 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u2_rev3
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family Spartan3 \
+device xc3s2000 \
+package fg456 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+control_lib/reset_sync.v \
+control_lib/priority_enc.v \
+control_lib/pic.v \
+vrt/vita_rx_control.v \
+vrt/vita_rx_framer.v \
+vrt/vita_tx_control.v \
+vrt/vita_tx_deframer.v \
+udp/udp_wrapper.v \
+udp/fifo19_rxrealign.v \
+udp/prot_eng_tx.v \
+udp/add_onescomp.v \
+simple_gemac/simple_gemac_wrapper.v \
+simple_gemac/simple_gemac_wrapper19.v \
+simple_gemac/simple_gemac.v \
+simple_gemac/simple_gemac_wb.v \
+simple_gemac/simple_gemac_tx.v \
+simple_gemac/simple_gemac_rx.v \
+simple_gemac/crc.v \
+simple_gemac/delay_line.v \
+simple_gemac/flow_ctrl_tx.v \
+simple_gemac/flow_ctrl_rx.v \
+simple_gemac/address_filter.v \
+simple_gemac/ll8_to_txmac.v \
+simple_gemac/rxmac_to_ll8.v \
+simple_gemac/miim/eth_miim.v \
+simple_gemac/miim/eth_clockgen.v \
+simple_gemac/miim/eth_outputcontrol.v \
+simple_gemac/miim/eth_shiftreg.v \
+control_lib/newfifo/buffer_int.v \
+control_lib/newfifo/buffer_pool.v \
+control_lib/newfifo/fifo_2clock.v \
+control_lib/newfifo/fifo_2clock_cascade.v \
+control_lib/newfifo/ll8_shortfifo.v \
+control_lib/newfifo/fifo_short.v \
+control_lib/newfifo/fifo_long.v \
+control_lib/newfifo/fifo_cascade.v \
+control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/newfifo/ll8_to_fifo36.v \
+control_lib/newfifo/fifo19_to_ll8.v \
+control_lib/newfifo/ll8_to_fifo19.v \
+control_lib/newfifo/fifo36_to_fifo19.v \
+control_lib/newfifo/fifo19_to_fifo36.v \
+control_lib/longfifo.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+coregen/fifo_xlnx_64x36_2clk.v \
+coregen/fifo_xlnx_64x36_2clk.xco \
+coregen/fifo_xlnx_16x19_2clk.v \
+coregen/fifo_xlnx_16x19_2clk.xco \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_64bit.v \
+timing/time_compare.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u2_rev3/u2_rev3.ucf \
+top/u2_rev3/u2_rev3.v 
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High 
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+	@echo make proj, check, synth, bin, or clean
+
+proj:
+	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
+
+check:
+	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
+
+synth:
+	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
+
+bin:
+	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+
diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf
new file mode 100644
index 000000000..255a298ac
--- /dev/null
+++ b/usrp2/top/u2_rev3/u2_rev3.ucf
@@ -0,0 +1,333 @@
+NET "leds[0]"  LOC = "E8"  ; 
+NET "leds[1]"  LOC = "F7"  ; 
+NET "leds[2]"  LOC = "E5"  ; 
+NET "leds[3]"  LOC = "B7"  ; 
+NET "leds[4]"  LOC = "C11"  ;
+NET "leds[5]"  LOC = "AB19"  ;
+NET "debug[0]"  LOC = "N5"  ;
+NET "debug[1]"  LOC = "N6"  ;
+NET "debug[2]"  LOC = "P1"  ;
+NET "debug[3]"  LOC = "P2"  ;
+NET "debug[4]"  LOC = "P4"  ;
+NET "debug[5]"  LOC = "P5"  ;
+NET "debug[6]"  LOC = "R1"  ;
+NET "debug[7]"  LOC = "R2"  ;
+NET "debug[8]"  LOC = "P6"  ;
+NET "debug[9]"  LOC = "R5"  ;
+NET "debug[10]"  LOC = "R4"  ;
+NET "debug[11]"  LOC = "T3"  ;
+NET "debug[12]"  LOC = "U3"  ;
+NET "debug[13]"  LOC = "M2"  ;
+NET "debug[14]"  LOC = "M3"  ;
+NET "debug[15]"  LOC = "M4"  ;
+NET "debug[16]"  LOC = "M5"  ;
+NET "debug[17]"  LOC = "M6"  ;
+NET "debug[18]"  LOC = "N1"  ;
+NET "debug[19]"  LOC = "N2"  ;
+NET "debug[20]"  LOC = "N3"  ;
+NET "debug[21]"  LOC = "T1"  ;
+NET "debug[22]"  LOC = "T2"  ;
+NET "debug[23]"  LOC = "U2"  ;
+NET "debug[24]"  LOC = "T4"  ;
+NET "debug[25]"  LOC = "U4"  ;
+NET "debug[26]"  LOC = "T5"  ;
+NET "debug[27]"  LOC = "T6"  ;
+NET "debug[28]"  LOC = "U5"  ;
+NET "debug[29]"  LOC = "V5"  ;
+NET "debug[30]"  LOC = "W2"  ;
+NET "debug[31]"  LOC = "W3"  ;
+NET "debug_clk[0]"  LOC = "N4"  ;
+NET "debug_clk[1]"  LOC = "M1"  ;
+NET "uart_tx_o"  LOC = "C7"  ;
+NET "uart_rx_i"  LOC = "A3"  ;
+NET "exp_pps_in_p"  LOC = "V3"  ; 
+NET "exp_pps_in_n"  LOC = "V4"  ; 
+NET "exp_pps_out_p"  LOC = "V1"  ; 
+NET "exp_pps_out_n"  LOC = "V2"  ; 
+NET "GMII_COL"  LOC = "U16"  ; 
+NET "GMII_CRS"  LOC = "U17"  ; 
+NET "GMII_TXD[0]"  LOC = "W14"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[1]"  LOC = "AA20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[2]"  LOC = "AB20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[3]"  LOC = "Y18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[4]"  LOC = "AA18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[5]"  LOC = "AB18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[6]"  LOC = "V17"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[7]"  LOC = "W17"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TX_EN"  LOC = "Y17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_TX_ER"  LOC = "V16" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_GTX_CLK"  LOC = "AA17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_TX_CLK"  LOC = "W13"  ; 
+NET "GMII_RXD[0]"  LOC = "AA15"  ;
+NET "GMII_RXD[1]"  LOC = "AB15"  ;
+NET "GMII_RXD[2]"  LOC = "U14"  ;
+NET "GMII_RXD[3]"  LOC = "V14"  ;
+NET "GMII_RXD[4]"  LOC = "U13"  ;
+NET "GMII_RXD[5]"  LOC = "V13"  ;
+NET "GMII_RXD[6]"  LOC = "Y13"  ;
+NET "GMII_RXD[7]"  LOC = "AA13"  ;
+NET "GMII_RX_CLK"  LOC = "AA12"  ; 
+NET "GMII_RX_DV"  LOC = "AB16"  ; 
+NET "GMII_RX_ER"  LOC = "AA16"  ; 
+NET "MDIO"  LOC = "Y16" |PULLUP ; 
+NET "MDC"  LOC = "V18"  ; 
+NET "PHY_INTn"  LOC = "AB13"  ; 
+NET "PHY_RESETn"  LOC = "AA19"  ; 
+NET "PHY_CLK"  LOC = "V15"  ; 
+NET "RAM_D[0]"  LOC = "N20"  ;
+NET "RAM_D[1]"  LOC = "N21"  ;
+NET "RAM_D[2]"  LOC = "N22"  ;
+NET "RAM_D[3]"  LOC = "M17"  ;
+NET "RAM_D[4]"  LOC = "M18"  ;
+NET "RAM_D[5]"  LOC = "M19"  ;
+NET "RAM_D[6]"  LOC = "M20"  ;
+NET "RAM_D[7]"  LOC = "M21"  ;
+NET "RAM_D[8]"  LOC = "M22"  ;
+NET "RAM_D[9]"  LOC = "Y22"  ;
+NET "RAM_D[10]"  LOC = "Y21"  ;
+NET "RAM_D[11]"  LOC = "Y20"  ;
+NET "RAM_D[12]"  LOC = "Y19"  ;
+NET "RAM_D[13]"  LOC = "W22"  ;
+NET "RAM_D[14]"  LOC = "W21"  ;
+NET "RAM_D[15]"  LOC = "W20"  ;
+NET "RAM_D[16]"  LOC = "W19"  ;
+NET "RAM_D[17]"  LOC = "V22"  ;
+NET "RAM_A[0]"  LOC = "U21"  ;
+NET "RAM_A[1]"  LOC = "T19"  ;
+NET "RAM_A[2]"  LOC = "V21"  ;
+NET "RAM_A[3]"  LOC = "V20"  ;
+NET "RAM_A[4]"  LOC = "T20"  ;
+NET "RAM_A[5]"  LOC = "T21"  ;
+NET "RAM_A[6]"  LOC = "T22"  ;
+NET "RAM_A[7]"  LOC = "T18"  ;
+NET "RAM_A[8]"  LOC = "R18"  ;
+NET "RAM_A[9]"  LOC = "P19"  ;
+NET "RAM_A[10]"  LOC = "P21"  ;
+NET "RAM_A[11]"  LOC = "P22"  ;
+NET "RAM_A[12]"  LOC = "N19"  ;
+NET "RAM_A[13]"  LOC = "N17"  ;
+NET "RAM_A[14]"  LOC = "N18"  ;
+NET "RAM_A[15]"  LOC = "T17"  ;
+NET "RAM_A[16]"  LOC = "U19"  ;
+NET "RAM_A[17]"  LOC = "U18"  ;
+NET "RAM_A[18]"  LOC = "V19"  ;
+NET "RAM_CE1n"  LOC = "U20"  ; 
+NET "RAM_CENn"  LOC = "P18"  ; 
+NET "RAM_CLK"  LOC = "P17"  ; 
+NET "RAM_WEn"  LOC = "R22"  ; 
+NET "RAM_OEn"  LOC = "R21"  ; 
+NET "RAM_LDn"  LOC = "R19"  ; 
+NET "ser_enable"  LOC = "W11"  ; 
+NET "ser_prbsen"  LOC = "AA3"  ; 
+NET "ser_loopen"  LOC = "Y4"  ; 
+NET "ser_rx_en"  LOC = "AB9"  ; 
+NET "ser_tx_clk"  LOC = "U7" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_t[0]"  LOC = "V7"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[1]"  LOC = "V10"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[2]"  LOC = "AB4"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[3]"  LOC = "AA4"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[4]"  LOC = "Y5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[5]"  LOC = "W5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[6]"  LOC = "AB5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[7]"  LOC = "AA5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[8]"  LOC = "W6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[9]"  LOC = "V6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[10]"  LOC = "AA6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[11]"  LOC = "Y6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[12]"  LOC = "W8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[13]"  LOC = "V8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[14]"  LOC = "AB8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[15]"  LOC = "AA8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_tklsb"  LOC = "U10" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_tkmsb"  LOC = "U11" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_rx_clk"  LOC = "AA11"  ; 
+NET "ser_r[0]"  LOC = "AB10"  ;
+NET "ser_r[1]"  LOC = "AA10"  ;
+NET "ser_r[2]"  LOC = "U9"  ;
+NET "ser_r[3]"  LOC = "U6"  ;
+NET "ser_r[4]"  LOC = "AB11"  ;
+NET "ser_r[5]"  LOC = "Y7"  ;
+NET "ser_r[6]"  LOC = "W7"  ;
+NET "ser_r[7]"  LOC = "AB7"  ;
+NET "ser_r[8]"  LOC = "AA7"  ;
+NET "ser_r[9]"  LOC = "W9"  ;
+NET "ser_r[10]"  LOC = "W10"  ;
+NET "ser_r[11]"  LOC = "Y1"  ;
+NET "ser_r[12]"  LOC = "Y3"  ;
+NET "ser_r[13]"  LOC = "Y2"  ;
+NET "ser_r[14]"  LOC = "W4"  ;
+NET "ser_r[15]"  LOC = "W1"  ;
+NET "ser_rklsb"  LOC = "V9"  ;
+NET "ser_rkmsb"  LOC = "Y10"  ; 
+NET "cpld_start"  LOC = "AA9"  ; 
+NET "cpld_mode"  LOC = "U12"  ; 
+NET "cpld_done"  LOC = "V12"  ; 
+NET "cpld_din"  LOC = "AA14"  ; 
+NET "cpld_clk"  LOC = "AB14"  ; 
+NET "cpld_detached"  LOC = "V11"  ;
+NET "cpld_init_b"  LOC = "W12"  ;
+NET "cpld_misc"  LOC = "Y12"  ;
+NET "POR"  LOC = "W18"  ;
+NET "WDI"  LOC = "W15"  ;
+NET "adc_a[0]"  LOC = "A14" | IOBDELAY= "NONE" ;
+NET "adc_a[1]"  LOC = "B14" | IOBDELAY= "NONE" ;
+NET "adc_a[2]"  LOC = "C13" | IOBDELAY= "NONE" ;
+NET "adc_a[3]"  LOC = "D13" | IOBDELAY= "NONE" ;
+NET "adc_a[4]"  LOC = "A13" | IOBDELAY= "NONE" ;
+NET "adc_a[5]"  LOC = "B13" | IOBDELAY= "NONE" ;
+NET "adc_a[6]"  LOC = "E12" | IOBDELAY= "NONE" ;
+NET "adc_a[7]"  LOC = "C22" | IOBDELAY= "NONE" ;
+NET "adc_a[8]"  LOC = "C20" | IOBDELAY= "NONE" ;
+NET "adc_a[9]"  LOC = "C21" | IOBDELAY= "NONE" ;
+NET "adc_a[10]"  LOC = "D20" | IOBDELAY= "NONE" ;
+NET "adc_a[11]"  LOC = "D19" | IOBDELAY= "NONE" ;
+NET "adc_a[12]"  LOC = "D21" | IOBDELAY= "NONE" ;
+NET "adc_a[13]"  LOC = "E18" | IOBDELAY= "NONE" ;
+NET "adc_ovf_a"  LOC = "F18"  ; 
+NET "adc_oen_a"  LOC = "E19"  ; 
+NET "adc_pdn_a"  LOC = "E20"  ; 
+NET "adc_b[0]"  LOC = "A12" | IOBDELAY= "NONE";
+NET "adc_b[1]"  LOC = "E16" | IOBDELAY= "NONE" ;
+NET "adc_b[2]"  LOC = "F12" | IOBDELAY= "NONE" ;
+NET "adc_b[3]"  LOC = "F13" | IOBDELAY= "NONE" ;
+NET "adc_b[4]"  LOC = "F16" | IOBDELAY= "NONE" ;
+NET "adc_b[5]"  LOC = "F17" | IOBDELAY= "NONE" ;
+NET "adc_b[6]"  LOC = "C19" | IOBDELAY= "NONE" ;
+NET "adc_b[7]"  LOC = "B20" | IOBDELAY= "NONE" ;
+NET "adc_b[8]"  LOC = "B19" | IOBDELAY= "NONE" ;
+NET "adc_b[9]"  LOC = "C18" | IOBDELAY= "NONE" ;
+NET "adc_b[10]"  LOC = "D18" | IOBDELAY= "NONE" ;
+NET "adc_b[11]"  LOC = "B18" | IOBDELAY= "NONE" ;
+NET "adc_b[12]"  LOC = "D17" | IOBDELAY= "NONE" ;
+NET "adc_b[13]"  LOC = "E17" | IOBDELAY= "NONE" ;
+NET "adc_ovf_b"  LOC = "B17"  ; 
+NET "adc_oen_b"  LOC = "C17"  ; 
+NET "adc_pdn_b"  LOC = "D15"  ; 
+NET "dac_a[0]"  LOC = "A5"  ;
+NET "dac_a[1]"  LOC = "B5"  ;
+NET "dac_a[2]"  LOC = "C5"  ;
+NET "dac_a[3]"  LOC = "D5"  ;
+NET "dac_a[4]"  LOC = "A4"  ;
+NET "dac_a[5]"  LOC = "B4"  ;
+NET "dac_a[6]"  LOC = "F6"  ;
+NET "dac_a[7]"  LOC = "D10"  ;
+NET "dac_a[8]"  LOC = "D9"  ;
+NET "dac_a[9]"  LOC = "A10"  ;
+NET "dac_a[10]"  LOC = "L2"  ;
+NET "dac_a[11]"  LOC = "L4"  ;
+NET "dac_a[12]"  LOC = "L3"  ;
+NET "dac_a[13]"  LOC = "L6"  ;
+NET "dac_a[14]"  LOC = "L5"  ;
+NET "dac_a[15]"  LOC = "K2"  ;
+NET "dac_b[0]"  LOC = "D11"  ;
+NET "dac_b[1]"  LOC = "E11"  ;
+NET "dac_b[2]"  LOC = "F11"  ;
+NET "dac_b[3]"  LOC = "B10"  ;
+NET "dac_b[4]"  LOC = "C10"  ;
+NET "dac_b[5]"  LOC = "E10"  ;
+NET "dac_b[6]"  LOC = "F10"  ;
+NET "dac_b[7]"  LOC = "A9"  ;
+NET "dac_b[8]"  LOC = "B9"  ;
+NET "dac_b[9]"  LOC = "E9"  ;
+NET "dac_b[10]"  LOC = "F9"  ;
+NET "dac_b[11]"  LOC = "A8"  ;
+NET "dac_b[12]"  LOC = "B8"  ;
+NET "dac_b[13]"  LOC = "D7"  ;
+NET "dac_b[14]"  LOC = "E7"  ;
+NET "dac_b[15]"  LOC = "B6"  ;
+NET "dac_lock"  LOC = "D6"  ;
+NET "SCL"  LOC = "A7"  ; 
+NET "SDA"  LOC = "D8"  ; 
+NET "clk_en[0]"  LOC = "C4"  ;
+NET "clk_en[1]"  LOC = "D1"  ;
+NET "clk_sel[0]"  LOC = "C3"  ;
+NET "clk_sel[1]"  LOC = "C2"  ;
+NET "clk_func"  LOC = "C12"  ; 
+NET "clk_status"  LOC = "B12"  ; 
+NET "clk_fpga_p"  LOC = "A11"  ; 
+NET "clk_fpga_n"  LOC = "B11"  ; 
+NET "clk_to_mac"  LOC = "AB12"  ; 
+NET "pps_in"  LOC = "K1"  ; 
+NET "sclk"  LOC = "K5"  ; 
+NET "sen_clk"  LOC = "K6"  ; 
+NET "sen_dac"  LOC = "L1"  ; 
+NET "sdi"  LOC = "J1"  ; 
+NET "sdo"  LOC = "J2"  ; 
+NET "sen_tx_db"  LOC = "C1"  ; 
+NET "sclk_tx_db"  LOC = "D3"  ; 
+NET "sdo_tx_db"  LOC = "G3"  ; 
+NET "sdi_tx_db"  LOC = "G4"  ; 
+NET "sen_tx_adc"  LOC = "G2"  ; 
+NET "sclk_tx_adc"  LOC = "H1"  ; 
+NET "sdo_tx_adc"  LOC = "H2"  ; 
+NET "sdi_tx_adc"  LOC = "J4"  ; 
+NET "sen_tx_dac"  LOC = "H4"  ; 
+NET "sclk_tx_dac"  LOC = "J5"  ; 
+NET "sdi_tx_dac"  LOC = "J6"  ; 
+NET "io_tx[0]"  LOC = "K4"  ;
+NET "io_tx[1]"  LOC = "K3"  ;
+NET "io_tx[2]"  LOC = "G1"  ;
+NET "io_tx[3]"  LOC = "G5"  ;
+NET "io_tx[4]"  LOC = "H5"  ;
+NET "io_tx[5]"  LOC = "F3"  ;
+NET "io_tx[6]"  LOC = "F2"  ;
+NET "io_tx[7]"  LOC = "F5"  ;
+NET "io_tx[8]"  LOC = "G6"  ;
+NET "io_tx[9]"  LOC = "E2"  ;
+NET "io_tx[10]"  LOC = "E1"  ;
+NET "io_tx[11]"  LOC = "E3"  ;
+NET "io_tx[12]"  LOC = "F4"  ;
+NET "io_tx[13]"  LOC = "D2"  ;
+NET "io_tx[14]"  LOC = "D4"  ;
+NET "io_tx[15]"  LOC = "E4"  ;
+NET "sen_rx_db"  LOC = "D22"  ; 
+NET "sclk_rx_db"  LOC = "F19"  ; 
+NET "sdo_rx_db"  LOC = "G20"  ; 
+NET "sdi_rx_db"  LOC = "H19"  ; 
+NET "sen_rx_adc"  LOC = "H18"  ; 
+NET "sclk_rx_adc"  LOC = "J17"  ; 
+NET "sdo_rx_adc"  LOC = "H21"  ; 
+NET "sdi_rx_adc"  LOC = "H22"  ; 
+NET "sen_rx_dac"  LOC = "J18"  ; 
+NET "sclk_rx_dac"  LOC = "J19"  ; 
+NET "sdi_rx_dac"  LOC = "J21"  ; 
+NET "io_rx[0]"  LOC = "L21"  ;
+NET "io_rx[1]"  LOC = "L20"  ;
+NET "io_rx[2]"  LOC = "L19"  ;
+NET "io_rx[3]"  LOC = "L18"  ;
+NET "io_rx[4]"  LOC = "L17"  ;
+NET "io_rx[5]"  LOC = "K22"  ;
+NET "io_rx[6]"  LOC = "K21"  ;
+NET "io_rx[7]"  LOC = "K20"  ;
+NET "io_rx[8]"  LOC = "G22"  ;
+NET "io_rx[9]"  LOC = "G21"  ;
+NET "io_rx[10]"  LOC = "F21"  ;
+NET "io_rx[11]"  LOC = "F20"  ;
+NET "io_rx[12]"  LOC = "G19"  ;
+NET "io_rx[13]"  LOC = "G18"  ;
+NET "io_rx[14]"  LOC = "G17"  ;
+NET "io_rx[15]"  LOC = "E22"  ;
+
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
+
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+
+NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
+
+#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
+#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
+#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+
+#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v
new file mode 100644
index 000000000..23a825007
--- /dev/null
+++ b/usrp2/top/u2_rev3/u2_rev3.v
@@ -0,0 +1,432 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2_rev3
+  (
+   // Misc, debug
+   output [5:0] leds,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+   output uart_tx_o,
+   input uart_rx_i,
+   
+   // Expansion
+   input exp_pps_in_p, // Diff
+   input exp_pps_in_n, // Diff
+   output exp_pps_out_p, // Diff 
+   output exp_pps_out_n, // Diff 
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output reg [7:0] GMII_TXD,
+   output reg GMII_TX_EN,
+   output reg GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+   input PHY_CLK,   // possibly use on-board osc
+
+   // RAM
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output reg [15:0] ser_t,
+   output reg ser_tklsb,
+   output reg ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output cpld_start,  // AA9
+   output cpld_mode,   // U12
+   output cpld_done,   // V12
+   input cpld_din,     // AA14 Now shared with CFG_Din
+   input cpld_clk,     // AB14 serial clock
+   input cpld_detached,// V11 unused
+   output cpld_init_b,  // W12 unused dual purpose
+   output cpld_misc,  // Y12 
+
+   // Watchdog interface
+   input POR,
+   output WDI,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_oen_a,
+   output adc_pdn_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_oen_b,
+   output adc_pdn_b,
+   
+   // DAC
+   output reg [15:0] dac_a,
+   output reg [15:0] dac_b,
+   input dac_lock,     // unused for now
+   
+   // I2C
+   inout SCL,
+   inout SDA,
+
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Clocks
+   input clk_fpga_p,  // Diff
+   input clk_fpga_n,  // Diff
+   input clk_to_mac,
+   input pps_in,
+   
+   // Generic SPI
+   output sclk,
+   output sen_clk,
+   output sen_dac,
+   output sdi,
+   input sdo,
+   
+   // TX DBoard
+   output sen_tx_db,
+   output sclk_tx_db,
+   input sdo_tx_db,
+   output sdi_tx_db,
+
+   output sen_tx_adc,
+   output sclk_tx_adc,
+   input sdo_tx_adc,
+   output sdi_tx_adc,
+
+   output sen_tx_dac,
+   output sclk_tx_dac,
+   output sdi_tx_dac,
+
+   inout [15:0] io_tx,
+
+   // RX DBoard
+   output sen_rx_db,
+   output sclk_rx_db,
+   input sdo_rx_db,
+   output sdi_rx_db,
+
+   output sen_rx_adc,
+   output sclk_rx_adc,
+   input sdo_rx_adc,
+   output sdi_rx_adc,
+
+   output sen_rx_dac,
+   output sclk_rx_dac,
+   output sdi_rx_dac,
+   
+   inout [15:0] io_rx   
+   );
+
+   assign 	cpld_init_b = 0;
+   // FPGA-specific pins connections
+   wire 	clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+   wire 	clk90, clk180, clk270;
+
+   // reset the watchdog continuously
+   reg [15:0] 	wd;
+   wire 	config_success;
+   
+   always @(posedge wb_clk)
+     if(~config_success)
+       wd <= 0;
+     else
+       wd <= wd + 1;
+   assign 	WDI = wd[15];
+   
+   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+   defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+   
+   wire 	exp_pps_in;
+   IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+   defparam 	exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+   
+   wire 	exp_pps_out;
+   OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+   defparam 	exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+   reg [5:0] 	clock_ready_d;
+   always @(posedge clk_fpga)
+     clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+   wire 	dcm_rst = ~&clock_ready_d & |clock_ready_d;
+   
+   wire 	adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+   assign 	adc_oen_a = ~adc_oe_a;
+   assign 	adc_oen_b = ~adc_oe_b;
+   assign 	adc_pdn_a = ~adc_on_a; 	
+   assign 	adc_pdn_b = ~adc_on_b; 	
+
+   reg [13:0] 	 adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
+   reg 		 adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
+
+   always @(posedge dsp_clk)
+     begin
+	adc_a_reg1 <= adc_a;
+	adc_b_reg1 <= adc_b;
+	adc_ovf_a_reg1 <= adc_ovf_a;
+	adc_ovf_b_reg1 <= adc_ovf_b;
+     end
+   
+   always @(posedge dsp_clk)
+     begin
+	adc_a_reg2 <= adc_a_reg1;
+	adc_b_reg2 <= adc_b_reg1;
+	adc_ovf_a_reg2 <= adc_ovf_a_reg1;
+	adc_ovf_b_reg2 <= adc_ovf_b_reg1;
+     end // always @ (posedge dsp_clk)
+
+   // Handle Clocks
+   DCM DCM_INST (.CLKFB(dsp_clk), 
+                 .CLKIN(clk_fpga), 
+                 .DSSEN(0), 
+                 .PSCLK(0), 
+                 .PSEN(0), 
+                 .PSINCDEC(0), 
+                 .RST(dcm_rst), 
+                 .CLKDV(clk_div), 
+                 .CLKFX(), 
+                 .CLKFX180(), 
+                 .CLK0(dcm_out), 
+                 .CLK2X(), 
+                 .CLK2X180(), 
+                 .CLK90(clk90), 
+                 .CLK180(clk180), 
+                 .CLK270(clk270), 
+                 .LOCKED(LOCKED_OUT), 
+                 .PSDONE(), 
+                 .STATUS());
+   defparam DCM_INST.CLK_FEEDBACK = "1X";
+   defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST.CLKFX_DIVIDE = 1;
+   defparam DCM_INST.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST.CLKIN_PERIOD = 10.000;
+   defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST.FACTORY_JF = 16'h8080;
+   defparam DCM_INST.PHASE_SHIFT = 0;
+   defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+   BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+   BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+   // I2C -- Don't use external transistors for open drain, the FPGA implements this
+   IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+   IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+   // LEDs are active low outputs
+   wire [5:0] leds_int;
+   assign     leds = 6'b011111 ^ leds_int;  // all except eth are active-low
+   
+   // SPI
+   wire 	miso, mosi, sclk_int;
+   assign 	{sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+   
+   assign 	miso = (~sen_clk & sdo) | (~sen_dac & sdo) | 
+		(~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+		(~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+   wire 	GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+   wire [7:0] 	GMII_TXD_unreg;
+   wire 	GMII_GTX_CLK_int;
+   
+   always @(posedge GMII_GTX_CLK_int)
+     begin
+	GMII_TX_EN <= GMII_TX_EN_unreg;
+	GMII_TX_ER <= GMII_TX_ER_unreg;
+	GMII_TXD <= GMII_TXD_unreg;
+     end
+
+   OFDDRRSE OFDDRRSE_gmii_inst 
+     (.Q(GMII_GTX_CLK),      // Data output (connect directly to top-level port)
+      .C0(GMII_GTX_CLK_int),    // 0 degree clock input
+      .C1(~GMII_GTX_CLK_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   
+   wire ser_tklsb_unreg, ser_tkmsb_unreg;
+   wire [15:0] ser_t_unreg;
+   wire        ser_tx_clk_int;
+   
+   always @(posedge ser_tx_clk_int)
+     begin
+	ser_tklsb <= ser_tklsb_unreg;
+	ser_tkmsb <= ser_tkmsb_unreg;
+	ser_t <= ser_t_unreg;
+     end
+
+   assign ser_tx_clk = clk_fpga;
+
+   reg [15:0] ser_r_int;
+   reg 	      ser_rklsb_int, ser_rkmsb_int;
+
+   always @(posedge ser_rx_clk)
+     begin
+	ser_r_int <= ser_r;
+	ser_rklsb_int <= ser_rklsb;
+	ser_rkmsb_int <= ser_rkmsb;
+     end
+
+   wire [15:0] dac_a_int, dac_b_int;
+   always @(negedge dsp_clk) dac_a <= dac_a_int;
+   always @(negedge dsp_clk) dac_b <= dac_b_int;
+
+   /*
+   OFDDRRSE OFDDRRSE_serdes_inst 
+     (.Q(ser_tx_clk),      // Data output (connect directly to top-level port)
+      .C0(ser_tx_clk_int),    // 0 degree clock input
+      .C1(~ser_tx_clk_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   */
+   u2_core #(.RAM_SIZE(32768))
+	u2_core(.dsp_clk           (dsp_clk),
+		     .wb_clk            (wb_clk),
+		     .clock_ready       (clock_ready),
+		     .clk_to_mac	(clk_to_mac),
+		     .pps_in		(pps_in),
+		     .leds		(leds_int),
+		     .debug		(debug[31:0]),
+		     .debug_clk		(debug_clk[1:0]),
+		     .exp_pps_in	(exp_pps_in),
+		     .exp_pps_out	(exp_pps_out),
+		     .GMII_COL		(GMII_COL),
+		     .GMII_CRS		(GMII_CRS),
+		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
+		     .GMII_TX_EN	(GMII_TX_EN_unreg),
+		     .GMII_TX_ER	(GMII_TX_ER_unreg),
+		     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
+		     .GMII_TX_CLK	(GMII_TX_CLK),
+		     .GMII_RXD		(GMII_RXD[7:0]),
+		     .GMII_RX_CLK	(GMII_RX_CLK),
+		     .GMII_RX_DV	(GMII_RX_DV),
+		     .GMII_RX_ER	(GMII_RX_ER),
+		     .MDIO		(MDIO),
+		     .MDC		(MDC),
+		     .PHY_INTn		(PHY_INTn),
+		     .PHY_RESETn	(PHY_RESETn),
+		     .ser_enable	(ser_enable),
+		     .ser_prbsen	(ser_prbsen),
+		     .ser_loopen	(ser_loopen),
+		     .ser_rx_en		(ser_rx_en),
+		     .ser_tx_clk	(ser_tx_clk_int),
+		     .ser_t		(ser_t_unreg[15:0]),
+		     .ser_tklsb		(ser_tklsb_unreg),
+		     .ser_tkmsb		(ser_tkmsb_unreg),
+		     .ser_rx_clk	(ser_rx_clk),
+		     .ser_r		(ser_r_int[15:0]),
+		     .ser_rklsb		(ser_rklsb_int),
+		     .ser_rkmsb		(ser_rkmsb_int),
+		     .cpld_start        (cpld_start),
+		     .cpld_mode         (cpld_mode),
+		     .cpld_done         (cpld_done),
+		     .cpld_din          (cpld_din),
+		     .cpld_clk          (cpld_clk),
+		     .cpld_detached     (cpld_detached),
+		     .cpld_misc         (cpld_misc),
+		     .cpld_init_b       (cpld_init_b),
+		     .por               (~POR),
+		     .config_success    (config_success),
+		     .adc_a		(adc_a_reg2),
+		     .adc_ovf_a		(adc_ovf_a_reg2),
+		     .adc_on_a		(adc_on_a),
+		     .adc_oe_a		(adc_oe_a),
+		     .adc_b		(adc_b_reg2),
+		     .adc_ovf_b		(adc_ovf_b_reg2),
+		     .adc_on_b		(adc_on_b),
+		     .adc_oe_b		(adc_oe_b),
+		     .dac_a		(dac_a_int),
+		     .dac_b		(dac_b_int),
+		     .scl_pad_i		(scl_pad_i),
+		     .scl_pad_o		(scl_pad_o),
+		     .scl_pad_oen_o	(scl_pad_oen_o),
+		     .sda_pad_i		(sda_pad_i),
+		     .sda_pad_o		(sda_pad_o),
+		     .sda_pad_oen_o	(sda_pad_oen_o),
+		     .clk_en		(clk_en[1:0]),
+		     .clk_sel		(clk_sel[1:0]),
+		     .clk_func		(clk_func),
+		     .clk_status	(clk_status),
+		     .sclk		(sclk_int),
+		     .mosi		(mosi),
+		     .miso		(miso),
+		     .sen_clk		(sen_clk),
+		     .sen_dac		(sen_dac),
+		     .sen_tx_db		(sen_tx_db),
+		     .sen_tx_adc	(sen_tx_adc),
+		     .sen_tx_dac	(sen_tx_dac),
+		     .sen_rx_db		(sen_rx_db),
+		     .sen_rx_adc	(sen_rx_adc),
+		     .sen_rx_dac	(sen_rx_dac),
+		     .io_tx		(io_tx[15:0]),
+		     .io_rx		(io_rx[15:0]),
+		     .RAM_D             (RAM_D),
+		     .RAM_A             (RAM_A),
+		     .RAM_CE1n          (RAM_CE1n),
+		     .RAM_CENn          (RAM_CENn),
+		     .RAM_CLK           (RAM_CLK),
+		     .RAM_WEn           (RAM_WEn),
+		     .RAM_OEn           (RAM_OEn),
+		     .RAM_LDn           (RAM_LDn), 
+		     .uart_tx_o         (uart_tx_o),
+		     .uart_rx_i         (uart_rx_i),
+		     .uart_baud_o       (),
+		     .sim_mode          (1'b0),
+		     .clock_divider     (2)
+		     );
+   
+endmodule // u2_rev2
diff --git a/usrp2/top/u2_rev3_2rx_iad/Makefile b/usrp2/top/u2_rev3_2rx_iad/Makefile
new file mode 100644
index 000000000..5b7ed5a8e
--- /dev/null
+++ b/usrp2/top/u2_rev3_2rx_iad/Makefile
@@ -0,0 +1,254 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u2_rev3
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family Spartan3 \
+device xc3s2000 \
+package fg456 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/buffer_int.v \
+control_lib/buffer_pool.v \
+control_lib/cascadefifo2.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/fifo_2clock.v \
+control_lib/fifo_2clock_casc.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/longfifo.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+eth/mac_rxfifo_int.v \
+eth/mac_txfifo_int.v \
+eth/rtl/verilog/Clk_ctrl.v \
+eth/rtl/verilog/MAC_rx.v \
+eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
+eth/rtl/verilog/MAC_rx/CRC_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
+eth/rtl/verilog/MAC_top.v \
+eth/rtl/verilog/MAC_tx.v \
+eth/rtl/verilog/MAC_tx/CRC_gen.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
+eth/rtl/verilog/MAC_tx/Random_gen.v \
+eth/rtl/verilog/Phy_int.v \
+eth/rtl/verilog/RMON.v \
+eth/rtl/verilog/RMON/RMON_addr_gen.v \
+eth/rtl/verilog/RMON/RMON_ctrl.v \
+eth/rtl/verilog/Reg_int.v \
+eth/rtl/verilog/eth_miim.v \
+eth/rtl/verilog/flow_ctrl_rx.v \
+eth/rtl/verilog/flow_ctrl_tx.v \
+eth/rtl/verilog/miim/eth_clockgen.v \
+eth/rtl/verilog/miim/eth_outputcontrol.v \
+eth/rtl/verilog/miim/eth_shiftreg.v \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/integrate.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_rev3/u2_rev3.ucf \
+top/u2_rev3/u2_rev3.v \
+top/u2_rev3_2rx_iad/u2_core.v \
+top/u2_rev3_2rx_iad/dsp_core_rx.v
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High 
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+	@echo make proj, check, synth, bin, testbench, or clean
+
+proj:
+	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
+
+check:
+	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
+
+synth:
+	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
+
+bin:
+	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
+
+testbench:
+	iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v
+
+clean:
+	rm -rf $(BUILD_DIR)
+	rm -f dsp_core_tb
+	rm -f *.lx2
+	rm -f *.dat
+	rm -f *.vcd
diff --git a/usrp2/top/u2_rev3_2rx_iad/README b/usrp2/top/u2_rev3_2rx_iad/README
new file mode 100644
index 000000000..3efc5305b
--- /dev/null
+++ b/usrp2/top/u2_rev3_2rx_iad/README
@@ -0,0 +1,32 @@
+This is a custom build for USRP2 FPGA.  It allows using a BasicRX or
+LFRX board and feed two independent, real signals.  In addition, instead
+of the CIC/HB decimator, which optimizes frequency response, it uses an
+integrate and dump decimator, which optimizes for time-domain impulse
+response.
+
+These changes have been made in dsp_core_rx.v:
+
+* A second DDC has been added, sharing a frequency register with
+  the existing DDC.
+
+* The output of the two DDCs are interleaved as I1 Q1 I2 Q2I ...
+  into the receive FIFO.  This limits the host configured decimation
+  to 8 intead of 4.  Use gr.deinterleave to recover the streams.
+
+* The ADCs are hardcoded:
+ 
+  RX_A ==>  DDC #1 I-input
+     0 ==>  DDC #1 Q-input
+  RX_B ==>  DDC #2 I-input
+     0 ==>  DDC #2 Q-input
+
+  Thus, the input mux has been disabled.
+
+* The CIC/HB decimator has been replaced by an integrate and dump at
+  the decimation rate.
+
+* To assist with meeting timing, the external RAM has been disabled.
+
+The basic application is to coherently sample two real IF streams and
+downconvert to baseband, while minimizing the impulse response duration
+of the resampling filters.
diff --git a/usrp2/top/u2_rev3_2rx_iad/cmdfile b/usrp2/top/u2_rev3_2rx_iad/cmdfile
new file mode 100644
index 000000000..34373a676
--- /dev/null
+++ b/usrp2/top/u2_rev3_2rx_iad/cmdfile
@@ -0,0 +1,4 @@
+-y .
+-y ../../sdr_lib
+-y ../../control_lib
+-y ../../models
diff --git a/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v b/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v
new file mode 100644
index 000000000..4a945bd1a
--- /dev/null
+++ b/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v
@@ -0,0 +1,212 @@
+`define DSP_CORE_RX_BASE 160
+module dsp_core_rx
+  (input clk, input rst,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   input [13:0] adc_a, input adc_ovf_a,
+   input [13:0] adc_b, input adc_ovf_b,
+   
+   input [15:0] io_rx,
+
+   output reg [31:0] sample,
+   input run,
+   output strobe,
+   output [31:0] debug
+   );
+
+   wire [15:0] scale_i, scale_q;
+   wire [13:0] adc_a_ofs, adc_b_ofs;
+   reg  [13:0] adc_i, adc_q;
+   wire [31:0] phase_inc;
+   reg  [31:0] phase;
+
+   wire [35:0] prod_i, prod_q;
+   wire [23:0] i_cordic_a, q_cordic_a, i_cordic_b, q_cordic_b;
+   wire [31:0] i_iad_a, q_iad_a, i_iad_b, q_iad_b;
+   wire [15:0] i_out_a, q_out_a, i_out_b, q_out_b;
+   
+   wire        enable_hb1, enable_hb2; // Correspond to std firmware settings
+   wire [7:0]  cic_decim;              // for combined CIC/HB decimator
+   wire [9:0]  decim_rate;             // Reconstructed original decimation setting
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_inc),.changed());
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({scale_i,scale_q}),.changed());
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed());
+
+   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_a),.adc_out(adc_a_ofs));
+   
+   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_b),.adc_out(adc_b_ofs));
+
+`ifdef MUXCTRL
+   wire [3:0]  muxctrl;
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(muxctrl),.changed());
+`endif
+   
+   wire [1:0] gpio_ena;
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(gpio_ena),.changed());
+
+   // The TVRX connects to what is called adc_b, thus A and B are
+   // swapped throughout the design.
+   //
+   // In the interest of expediency and keeping the s/w sane, we just remap them here.
+   // The I & Q fields are mapped the same:
+   // 0 -> "the real A" (as determined by the TVRX)
+   // 1 -> "the real B"
+   // 2 -> const zero
+
+`ifdef MUXCTRL   
+   always @(posedge clk)
+     case(muxctrl[1:0])		// The I mapping
+       0: adc_i <= adc_b_ofs;	// "the real A"
+       1: adc_i <= adc_a_ofs;
+       2: adc_i <= 0;
+       default: adc_i <= 0;
+     endcase // case(muxctrl[1:0])
+          
+   always @(posedge clk)
+     case(muxctrl[3:2])		// The Q mapping
+       0: adc_q <= adc_b_ofs;	// "the real A"
+       1: adc_q <= adc_a_ofs;
+       2: adc_q <= 0;
+       default: adc_q <= 0;
+     endcase // case(muxctrl[3:2])
+`else // !`ifdef MUXCTRL
+   always @(posedge clk)
+     begin
+	adc_i <= adc_a_ofs;
+	adc_q <= adc_b_ofs;
+     end
+`endif // !`ifdef MUXCTRL
+   
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(~run)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+
+   MULT18X18S mult_i
+     (.P(prod_i),    // 36-bit multiplier output
+      .A({{4{adc_i[13]}},adc_i} ),    // 18-bit multiplier input
+      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      );
+
+   MULT18X18S mult_q
+     (.P(prod_q),    // 36-bit multiplier output
+      .A({{4{adc_q[13]}},adc_q} ),    // 18-bit multiplier input
+      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      ); 
+
+   
+   // Route I,0 to first CORDIC
+   cordic_z24 #(.bitwidth(24))
+     cordic_a(.clock(clk), .reset(rst), .enable(run),
+	      .xi(prod_i[24:1]),. yi(0), .zi(phase[31:8]),
+	      .xo(i_cordic_a),.yo(q_cordic_a),.zo() );
+
+   // Route Q,0 to second CORDIC
+   cordic_z24 #(.bitwidth(24))
+     cordic_b(.clock(clk), .reset(rst), .enable(run),
+	      .xi(prod_q[24:1]),. yi(0), .zi(phase[31:8]),
+	      .xo(i_cordic_b),.yo(q_cordic_b),.zo() );
+
+   // Reconstruct original decimation rate from standard firmware settings
+   assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : 
+                                                  {1'b0,cic_decim,1'b0 }) :
+				    cic_decim;
+
+   cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator
+   cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate),
+	       .strobe_fast(1),.strobe_slow(strobe_iad) );
+
+   wire       strobe_iad_o;
+   
+   integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_a
+     (.clk_i(clk),.rst_i(rst),.ena_i(run),
+      .dump_i(strobe_iad),.data_i(i_cordic_a),
+      .stb_o(strobe_iad_o),.integ_o(i_iad_a) );
+
+   integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_a
+     (.clk_i(clk),.rst_i(rst),.ena_i(run),
+      .dump_i(strobe_iad),.data_i(q_cordic_a),
+      .stb_o(),.integ_o(q_iad_a) );
+   
+   integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_b
+     (.clk_i(clk),.rst_i(rst),.ena_i(run),
+      .dump_i(strobe_iad),.data_i(i_cordic_b),
+      .stb_o(),.integ_o(i_iad_b) );
+
+   integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_b
+     (.clk_i(clk),.rst_i(rst),.ena_i(run),
+      .dump_i(strobe_iad),.data_i(q_cordic_b),
+      .stb_o(),.integ_o(q_iad_b) );
+   
+   round #(.bits_in(32),.bits_out(16)) round_iout_a (.in(i_iad_a),.out(i_out_a));
+   round #(.bits_in(32),.bits_out(16)) round_qout_a (.in(q_iad_a),.out(q_out_a));
+   round #(.bits_in(32),.bits_out(16)) round_iout_b (.in(i_iad_b),.out(i_out_b));
+   round #(.bits_in(32),.bits_out(16)) round_qout_b (.in(q_iad_b),.out(q_out_b));
+
+   reg [31:0]  sample_out_a, sample_out_b, sample_out;
+   reg 	       stb_d1, stb_d2, stb_d3, stb_d4, stb_d5;
+   reg         strobe_out;
+   
+   // Register samples on strobe_iad
+   // Output A on d1
+   // Output B on d5
+   always @(posedge clk)
+     begin
+	stb_d1 <= strobe_iad_o;
+	stb_d2 <= stb_d1;
+	stb_d3 <= stb_d2;
+	stb_d4 <= stb_d3;
+	stb_d5 <= stb_d4;
+     end
+   
+   always @(posedge clk)
+     if (strobe_iad_o)
+       begin	
+	  // Streaming GPIO
+	  // io_rx[15] => I channel LSB if gpio_ena[0] high
+	  // io_rx[14] => Q channel LSB if gpio_ena[1] high
+	  sample_out_a <= {i_out_a[15:1], gpio_ena[0] ? io_rx[15] : i_out_a[0],
+			   q_out_a[15:1], gpio_ena[1] ? io_rx[14] : q_out_a[0] };
+	  sample_out_b <= {i_out_b[15:1], gpio_ena[0] ? io_rx[15] : i_out_b[0],
+			   q_out_b[15:1], gpio_ena[1] ? io_rx[14] : q_out_b[0] };
+       end
+
+   always @(posedge clk)
+     begin
+	if (stb_d1)
+	  sample <= sample_out_a;
+	else if (stb_d5)
+	  sample <= sample_out_b;
+	strobe_out <= stb_d1|stb_d5;
+     end
+
+   assign strobe = strobe_out;
+   assign debug = 0;
+      
+endmodule // dsp_core_rx
diff --git a/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav b/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav
new file mode 100644
index 000000000..12f746860
--- /dev/null
+++ b/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav
@@ -0,0 +1,106 @@
+[size] 1680 975
+[pos] -1 -1
+*-17.007835 70679400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] dsp_core_tb.
+@200
+-SYSCON
+@28
+dsp_core_tb.clk
+dsp_core_tb.rst
+dsp_core_tb.run
+@200
+-
+-Settings Bus
+@22
+dsp_core_tb.set_addr[7:0]
+@24
+dsp_core_tb.set_data[31:0]
+@28
+dsp_core_tb.set_stb
+@200
+-
+-RX DSP CORE
+@22
+dsp_core_tb.rx_path.adc_a[13:0]
+dsp_core_tb.rx_path.adc_b[13:0]
+@28
+dsp_core_tb.rx_path.adc_ovf_a
+dsp_core_tb.rx_path.adc_ovf_b
+@22
+dsp_core_tb.rx_path.io_rx[15:0]
+@200
+-
+@22
+dsp_core_tb.rx_path.sample[31:0]
+@28
+dsp_core_tb.rx_path.strobe
+@200
+-
+@22
+dsp_core_tb.rx_path.phase_inc[31:0]
+dsp_core_tb.rx_path.scale_i[15:0]
+dsp_core_tb.rx_path.scale_q[15:0]
+@28
+dsp_core_tb.rx_path.enable_hb1
+dsp_core_tb.rx_path.enable_hb2
+@22
+dsp_core_tb.rx_path.cic_decim[7:0]
+dsp_core_tb.rx_path.adc_a_ofs[13:0]
+dsp_core_tb.rx_path.adc_b_ofs[13:0]
+dsp_core_tb.rx_path.muxctrl[3:0]
+@200
+-
+@22
+dsp_core_tb.rx_path.adc_i[13:0]
+dsp_core_tb.rx_path.adc_q[13:0]
+dsp_core_tb.rx_path.phase[31:0]
+dsp_core_tb.rx_path.prod_i[35:0]
+dsp_core_tb.rx_path.prod_q[35:0]
+@8420
+dsp_core_tb.rx_path.i_cordic_a[23:0]
+dsp_core_tb.rx_path.q_cordic_a[23:0]
+dsp_core_tb.rx_path.i_cordic_b[23:0]
+dsp_core_tb.rx_path.q_cordic_b[23:0]
+@22
+dsp_core_tb.rx_path.decim_rate[9:0]
+@28
+dsp_core_tb.rx_path.strobe_iad
+@22
+dsp_core_tb.rx_path.i_iad_a[31:0]
+dsp_core_tb.rx_path.q_iad_a[31:0]
+@23
+dsp_core_tb.rx_path.i_iad_b[31:0]
+@22
+dsp_core_tb.rx_path.q_iad_b[31:0]
+@28
+dsp_core_tb.rx_path.strobe_iad_o
+@8420
+dsp_core_tb.rx_path.i_out_a[15:0]
+dsp_core_tb.rx_path.q_out_a[15:0]
+dsp_core_tb.rx_path.i_out_b[15:0]
+dsp_core_tb.rx_path.q_out_b[15:0]
+@28
+dsp_core_tb.rx_path.gpio_ena[1:0]
+@22
+dsp_core_tb.rx_path.sample_out_a[31:0]
+dsp_core_tb.rx_path.sample_out_b[31:0]
+dsp_core_tb.rx_path.sample[31:0]
+@28
+dsp_core_tb.rx_path.strobe_out
+dsp_core_tb.rx_path.stb_d1
+dsp_core_tb.rx_path.stb_d2
+dsp_core_tb.rx_path.stb_d3
+dsp_core_tb.rx_path.stb_d4
+dsp_core_tb.rx_path.stb_d5
+@200
+-
+-FIFO Bus
+@22
+dsp_core_tb.master_time[31:0]
+dsp_core_tb.wr_dat[31:0]
+@28
+dsp_core_tb.wr_done
+dsp_core_tb.wr_error
+dsp_core_tb.wr_full
+dsp_core_tb.wr_ready
+dsp_core_tb.wr_write
diff --git a/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v b/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v
new file mode 100644
index 000000000..d947df40a
--- /dev/null
+++ b/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v
@@ -0,0 +1,233 @@
+`timescale 1ns / 100ps
+
+module dsp_core_tb;
+
+///////////////////////////////////////////////////////////////////////////////////
+// Sim-wide wires/busses                                                         //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   // System control bus
+   reg                clk = 0;
+   reg                rst = 1;
+   
+   // Configuration bus
+   reg                set_stb = 0;  
+   reg          [7:0] set_addr = 0; 
+   reg         [31:0] set_data = 0; 
+
+   // ADC input bus
+   wire signed [13:0] adc_a;
+   wire signed [13:0] adc_b;
+   wire               adc_ovf_a;
+   wire               adc_ovf_b;
+   
+   // RX sample bus
+   reg                run = 1;
+   wire        [31:0] sample;
+   wire               stb;
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Simulation control                                                            //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   // Set up output files
+   initial begin
+      $dumpfile("dsp_core_tb.vcd");
+      $dumpvars(0,dsp_core_tb);
+   end
+
+   // Update display every 10 us
+   always #1000 $monitor("Time in us ",$time/1000);
+
+   // Generate master clock 50% @ 100 MHz
+   always
+     #5 clk = ~clk;
+
+///////////////////////////////////////////////////////////////////////////////////
+// Unit(s) under test                                                            //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   reg [13:0] amplitude = 13'h1fff;
+   reg [15:0] impulse_len = 0;
+   reg [15:0] zero_len = 0;
+   reg 	      adc_ena = 0;
+
+   initial #500 @(posedge clk) adc_ena = 1;
+
+   impulse adc
+     (.clk(clk),.rst(rst),.ena(adc_ena),
+      .dc_offset_a(0),.dc_offset_b(0),
+      .amplitude(amplitude),
+      .impulse_len(impulse_len),.zero_len(zero_len),
+      .adc_a(adc_a),.adc_b(adc_b),
+      .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) );
+
+   initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's
+   initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset
+   dsp_core_rx rx_path
+     (.clk(clk),.rst(rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),
+      .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .io_rx(16'b0),
+      .run(adc_ena),.sample(sample),.strobe(stb),
+      .debug() );
+
+   reg  [31:0] master_time = 0;
+   always @(posedge clk)
+     master_time <= master_time + 1;
+
+   reg         wr_ready    = 1;
+   reg         wr_full     = 0;
+
+   wire [31:0] wr_dat;
+   wire        wr_write;
+   wire        wr_done;
+   wire        wr_error;
+   wire [15:0] fifo_occupied;
+   wire        fifo_full;
+   wire        fifo_empty;
+   
+   rx_control rx_buffer
+    (.clk(clk),.rst(rst),
+     .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+     .master_time(master_time),
+     .overrun(), // unconnected output
+     .wr_dat_o(wr_dat),
+     .wr_write_o(wr_write),
+     .wr_done_o(wr_done),
+     .wr_error_o(wr_error),
+     .wr_ready_i(wr_ready),
+     .wr_full_i(wr_full),
+     .sample(sample),
+     .run(), // unconnected output, supposed to drive 'run'
+     .strobe(stb),
+     .fifo_occupied(fifo_occupied),
+     .fifo_full(fifo_full),
+     .fifo_empty(fifo_empty),
+     .debug_rx() // unconnected output
+     );
+
+
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Simulation output/checking                                                    //
+///////////////////////////////////////////////////////////////////////////////////
+
+   integer rx_file;
+   
+   initial
+     rx_file = $fopen("rx.dat", "wb");
+   
+   always @(posedge clk)
+     begin
+	// Write RX sample I&Q in format Octave can load
+	if (stb)
+	  begin
+	     $fwrite(rx_file, sample[31:16]);
+	     $fputc(32, rx_file);
+	     $fwrite(rx_file, sample[15:0]);
+	     $fputc(13, rx_file);
+	  end
+     end
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Tasks                                                                         //
+///////////////////////////////////////////////////////////////////////////////////
+
+   task power_on;
+     begin
+	@(posedge clk)
+	  rst = #1 1'b1;
+	@(posedge clk)
+	  rst = #1 1'b0;
+     end
+   endtask // power_on
+   
+   task set_impulse_len;
+      input [15:0] len;
+      @(posedge clk) impulse_len = len-1;
+   endtask
+ 
+   task set_zero_len;
+      input [15:0] len;
+      @(posedge clk) zero_len = len-1;
+   endtask
+
+   // Strobe configuration bus with addr, data
+   task write_cfg_register;
+      input [7:0]  regno;
+      input [31:0] value;
+      
+      begin
+	 @(posedge clk);
+	 set_addr <= regno;
+	 set_data <= value;
+	 set_stb  <= 1'b1;
+	 @(posedge clk);
+	 set_stb  <= 1'b0;
+      end
+   endtask // write_cfg_register
+
+   // Set RX DDC frequency
+   task set_ddc_freq;
+      input [31:0] freq;
+
+      write_cfg_register(160, freq);
+   endtask // set_ddc_freq
+
+   // Set RX IQ scaling registers
+   task set_rx_scale_iq;
+      input [15:0] scale_i;
+      input [15:0] scale_q;
+
+      write_cfg_register(161, {scale_i,scale_q});
+   endtask // set_rx_scale_iq
+   
+   // Set RX MUX control
+   task set_rx_muxctrl;
+      input [3:0] muxctrl;
+
+      write_cfg_register(168, muxctrl);
+   endtask // set_rx_muxctrl
+   
+   // Set RX CIC decim and halfband enables
+   task set_decim;
+      input hb1_ena;
+      input hb2_ena;
+      input [7:0] decim;
+
+      write_cfg_register(162, {hb1_ena,hb2_ena,decim});
+   endtask // set_decim
+      
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Individual tests                                                              //
+///////////////////////////////////////////////////////////////////////////////////
+
+   task test_rx;
+      begin
+	 set_impulse_len(10);
+	 set_zero_len(990);
+	 set_rx_muxctrl(1);
+	 set_ddc_freq(32'h10000000);
+	 set_rx_scale_iq(1243, 1243);
+	 set_decim(1, 1, 1);
+
+	 #100000 $finish;
+      end
+   endtask // test_rx
+   
+      
+///////////////////////////////////////////////////////////////////////////////////
+// Top-level test                                                                //
+///////////////////////////////////////////////////////////////////////////////////
+
+   // Execute tests
+   initial
+     begin
+	power_on();
+	test_rx();
+     end
+
+endmodule // dsp_core_tb
diff --git a/usrp2/top/u2_rev3_2rx_iad/impulse.v b/usrp2/top/u2_rev3_2rx_iad/impulse.v
new file mode 100644
index 000000000..fc5e3c1ed
--- /dev/null
+++ b/usrp2/top/u2_rev3_2rx_iad/impulse.v
@@ -0,0 +1,68 @@
+module impulse
+  (input clk,
+   input rst,
+   input ena,
+   
+   input [13:0] dc_offset_a,
+   input [13:0] dc_offset_b,
+   input [13:0] amplitude,
+   input [15:0] impulse_len,
+   input [15:0] zero_len,
+
+   output [13:0] adc_a,
+   output [13:0] adc_b,
+   output        adc_ovf_a,
+   output        adc_ovf_b
+   );
+
+   reg [13:0] adc_a_int = 0;
+   reg [13:0] adc_b_int = 0;
+   
+   reg [15:0] count;
+
+   localparam ST_ZERO = 0;
+   localparam ST_HIGH = 1;
+   reg 	      state;
+   
+   always @(posedge clk)
+     if (rst | ~ena)
+       begin
+	  adc_a_int <= 0;
+	  adc_b_int <= 0;
+	  count <= 0;
+	  state <= ST_ZERO;
+       end
+     else
+       case(state)
+	 ST_ZERO:
+	   if (count == zero_len)
+	     begin
+		adc_a_int <= amplitude;
+		adc_b_int <= amplitude >> 2;
+		state <= ST_HIGH;
+		count <= 0;
+	     end
+	   else
+	     count <= count + 1;
+
+	 ST_HIGH:
+	   if (count == impulse_len)
+	     begin
+		adc_a_int <= 0;
+		adc_b_int <= 0;
+		state <= ST_ZERO;
+		count <= 0;
+	     end
+	   else
+	     count <= count + 1;
+
+       endcase // case (state)
+
+   assign adc_a = adc_a_int + dc_offset_a;
+   assign adc_b = adc_b_int + dc_offset_b;
+
+   // Ignore for now
+   assign adc_ovf_a = 0;
+   assign adc_ovf_b = 0;
+
+endmodule // impulse
diff --git a/usrp2/top/u2_rev3_2rx_iad/u2_core.v b/usrp2/top/u2_rev3_2rx_iad/u2_core.v
new file mode 100755
index 000000000..3d96a4e0e
--- /dev/null
+++ b/usrp2/top/u2_rev3_2rx_iad/u2_core.v
@@ -0,0 +1,789 @@
+// ////////////////////////////////////////////////////////////////////////////////
+// Module Name:    u2_core
+// ////////////////////////////////////////////////////////////////////////////////
+
+module u2_core
+  #(parameter RAM_SIZE=32768)
+  (// Clocks
+   input dsp_clk,
+   input wb_clk,
+   output clock_ready,
+   input clk_to_mac,
+   input pps_in,
+   
+   // Misc, debug
+   output [7:0] leds,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+
+   // Expansion
+   input exp_pps_in,
+   output exp_pps_out,
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output [7:0] GMII_TXD,
+   output GMII_TX_EN,
+   output GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output [15:0] ser_t,
+   output ser_tklsb,
+   output ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output cpld_start,
+   output cpld_mode,
+   output cpld_done,
+   input cpld_din,
+   input cpld_clk,
+   input cpld_detached,
+   output cpld_misc,
+   input cpld_init_b,
+   input por,
+   output config_success,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_on_a,
+   output adc_oe_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_on_b,
+   output adc_oe_b,
+   
+   // DAC
+   output [15:0] dac_a,
+   output [15:0] dac_b,
+
+   // I2C
+   input scl_pad_i,
+   output scl_pad_o,
+   output scl_pad_oen_o,
+   input sda_pad_i,
+   output sda_pad_o,
+   output sda_pad_oen_o,
+   
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Generic SPI
+   output sclk,
+   output mosi,
+   input miso,
+   output sen_clk,
+   output sen_dac,
+   output sen_tx_db,
+   output sen_tx_adc,
+   output sen_tx_dac,
+   output sen_rx_db,
+   output sen_rx_adc,
+   output sen_rx_dac,
+   
+   // GPIO to DBoards
+   inout [15:0] io_tx,
+   inout [15:0] io_rx,
+
+   // External RAM
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // Debug stuff
+   output uart_tx_o, 
+   input uart_rx_i,
+   output uart_baud_o,
+   input sim_mode,
+   input [3:0] clock_divider
+   );
+   
+   wire [7:0] 	set_addr;
+   wire [31:0] 	set_data;
+   wire 	set_stb;
+   
+   wire 	ram_loader_done;
+   wire 	ram_loader_rst, wb_rst, dsp_rst;
+
+   wire [31:0] 	status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
+   wire 	bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
+
+   wire [31:0] 	debug_gpio_0, debug_gpio_1;
+   wire [31:0] 	atr_lines;
+
+   wire [31:0] 	debug_rx, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, 
+		debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp;
+
+   wire [15:0] 	ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
+   wire 	ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
+   wire 	ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2;
+	
+   wire 	serdes_link_up;
+   wire 	epoch;
+   
+   // ///////////////////////////////////////////////////////////////////////////////////////////////
+   // Wishbone Single Master INTERCON
+   localparam 	dw = 32;  // Data bus width
+   localparam 	aw = 16;  // Address bus width, for byte addressibility, 16 = 64K byte memory space
+   localparam	sw = 4;   // Select width -- 32-bit data bus with 8-bit granularity.  
+   
+   wire [dw-1:0] m0_dat_o, m0_dat_i;
+   wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
+		 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
+		 s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o,
+		 s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o;
+   wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr;
+   wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel;
+   wire 	 m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack;
+   wire 	 m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb;
+   wire 	 m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc;
+   wire 	 m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err;
+   wire 	 m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty;
+   wire 	 m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we;
+   
+   wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10),
+		.s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10),
+		.s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10),
+		.s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10),
+		.s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01),
+		.dw(dw),.aw(aw),.sw(sw)) wb_1master
+     (.clk_i(wb_clk),.rst_i(wb_rst),       
+      .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
+      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+      .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o	(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+      .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty),
+      .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o	(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+      .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty),
+      .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o	(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+      .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty),
+      .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o	(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+      .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty),
+      .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o	(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+      .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty),
+      .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o	(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+      .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty),
+      .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o	(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+      .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty),
+      .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o	(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+      .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty),
+      .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o	(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
+      .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty),
+      .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o	(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
+      .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty),
+      .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb),
+      .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty),
+      .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb),
+      .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty),
+      .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb),
+      .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty),
+      .s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb),
+      .s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty),
+      .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb),
+      .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty),
+      .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0)  );
+   
+   //////////////////////////////////////////////////////////////////////////////////////////
+   // Reset Controller
+   system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por),
+			   .ram_loader_rst_o(ram_loader_rst),
+			   .wb_rst_o(wb_rst),
+			   .ram_loader_done_i(ram_loader_done));
+
+   assign 	 config_success = ram_loader_done;
+   reg 		 takeover = 0;
+
+   wire 	 cpld_start_int, cpld_mode_int, cpld_done_int;
+   
+   always @(posedge wb_clk)
+     if(ram_loader_done)
+       takeover = 1;
+   assign 	 cpld_misc = ~takeover;
+
+   wire 	 sd_clk, sd_csn, sd_mosi, sd_miso;
+   
+   assign 	 sd_miso = cpld_din;
+   assign 	 cpld_start = takeover ? sd_clk	: cpld_start_int;
+   assign 	 cpld_mode = takeover ? sd_csn : cpld_mode_int;
+   assign 	 cpld_done = takeover ? sd_mosi : cpld_done_int;
+   
+   // ///////////////////////////////////////////////////////////////////
+   // RAM Loader
+
+   wire [31:0] 	 ram_loader_dat, iwb_dat;
+   wire [15:0] 	 ram_loader_adr, iwb_adr;
+   wire [3:0] 	 ram_loader_sel;
+   wire 	 ram_loader_stb, ram_loader_we, ram_loader_ack;
+   wire 	 iwb_ack, iwb_stb;
+   ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
+     ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+		 // CPLD Interface
+		 .cfg_clk_i(cpld_clk),
+		 .cfg_data_i(cpld_din),
+		 .start_o(cpld_start_int),
+		 .mode_o(cpld_mode_int),
+		 .done_o(cpld_done_int),
+		 .detached_i(cpld_detached),
+		 // Wishbone Interface
+		 .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
+		 .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
+		 .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
+		 .ram_loader_done_o(ram_loader_done));
+
+   // Processor
+   aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
+     aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
+	   // Instruction Wishbone bus to I-RAM
+	   .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
+	   .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
+	   // Data Wishbone bus to system bus fabric
+	   .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
+	   .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
+	   // Interrupts and exceptions
+	   .sys_int_i(proc_int),.sys_exc_i(bus_error) );
+   
+   assign 	 bus_error = m0_err | m0_rty;
+   
+   // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
+   // I-port connects directly to processor and ram loader
+
+   wire 	 flush_icache;
+   ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
+     sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+	     
+	     .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
+	     .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
+	     .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
+	     .ram_loader_done_i(ram_loader_done),
+	     
+	     .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
+	     .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
+	     
+	     .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
+	     .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
+	     .flush_icache(flush_icache));
+   
+   assign 	 s0_err = 1'b0;
+   assign 	 s0_rty = 1'b0;
+
+   setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+					 .in(set_data),.out(),.changed(flush_icache));
+
+   // Buffer Pool, slave #1
+   wire 	 rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop;
+   wire 	 rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop;
+   wire 	 rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop;
+   wire 	 rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop;
+   wire [31:0] 	 rd0_dat, rd1_dat, rd2_dat, rd3_dat;
+
+   wire 	 wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full;
+   wire 	 wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full;
+   wire 	 wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full;
+   wire 	 wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full;
+   wire [31:0] 	 wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+   
+   buffer_pool buffer_pool
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+      .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),   
+      .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty),
+   
+      .stream_clk(dsp_clk), .stream_rst(dsp_rst),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .status(status),.sys_int_o(buffer_int),
+
+      .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
+      .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
+      
+      // Write Interfaces
+      .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done),
+      .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full),
+      .wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done),
+      .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full),
+      .wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done),
+      .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full),
+      .wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done),
+      .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full),
+      // Read Interfaces
+      .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done),
+      .rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop),
+      .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done),
+      .rd1_error_i(rd1_error), .rd1_sop_o(rd1_sop), .rd1_eop_o(rd1_eop),
+      .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done),
+      .rd2_error_i(rd2_error), .rd2_sop_o(rd2_sop), .rd2_eop_o(rd2_eop),
+      .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done),
+      .rd3_error_i(rd3_error), .rd3_sop_o(rd3_sop), .rd3_eop_o(rd3_eop)
+      );
+
+   // SPI -- Slave #2
+   spi_top shared_spi
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
+      .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
+      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int),
+      .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+      .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+
+   assign 	 s2_rty = 1'b0;
+   
+   // I2C -- Slave #3
+   i2c_master_top #(.ARST_LVL(1)) 
+     i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
+	  .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
+	  .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+	  .wb_ack_o(s3_ack),.wb_inta_o(i2c_int),
+	  .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+	  .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+   assign 	 s3_dat_i[31:8] = 24'd0;
+   assign 	 s3_err = 1'b0;
+   assign 	 s3_rty = 1'b0;
+   
+   // GPIOs -- Slave #4
+   nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
+		 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
+		 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
+		 .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+		 .gpio( {io_tx,io_rx} ) );
+   assign 	 s4_err = 1'b0;
+   assign 	 s4_rty = 1'b0;
+
+   // Buffer Pool Status -- Slave #5
+   wb_readback_mux buff_pool_status
+     (.wb_clk_i(wb_clk),
+      .wb_rst_i(wb_rst),
+      .wb_stb_i(s5_stb),
+      .wb_adr_i(s5_adr),
+      .wb_dat_o(s5_dat_i),
+      .wb_ack_o(s5_ack),
+      
+      .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
+      .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
+      .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0),
+      .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
+      );
+
+   assign 	 s5_err = 1'b0;
+   assign 	 s5_rty = 1'b0;
+
+   // Slave, #6 Ethernet MAC, see below
+   
+   // Settings Bus -- Slave #7
+   settings_bus settings_bus
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
+      .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
+      .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
+   
+   assign 	 s7_err = 1'b0;
+   assign 	 s7_rty = 1'b0;
+   assign 	 s7_dat_i = 32'd0;
+
+   // Output control lines
+   wire [7:0] 	 clock_outs, serdes_outs, adc_outs;
+   assign 	 {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
+   assign 	 {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
+   assign 	 {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0];
+
+   wire 	 phy_reset;
+   assign 	 PHY_RESETn = ~phy_reset;
+   
+   setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
+				      .in(set_data),.out(clock_outs),.changed());
+   setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(serdes_outs),.changed());
+   setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(adc_outs),.changed());
+   setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(phy_reset),.changed());
+
+   // /////////////////////////////////////////////////////////////////////////
+   //  LEDS
+   //    register 8 determines whether leds are controlled by SW or not
+   //    1 = controlled by HW, 0 = by SW
+   //    In Rev3 there are only 6 leds, and the highest one is on the ETH connector
+   
+   wire [7:0] 	 led_src, led_sw;
+   wire [7:0] 	 led_hw = {clk_status,serdes_link_up};
+   
+   setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(led_sw),.changed());
+   setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+					  .in(set_data),.out(led_src),.changed());
+
+   assign 	 leds = (led_src & led_hw) | (~led_src & led_sw);
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Ethernet MAC  Slave #6
+   
+   wire 	 Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop;
+   wire 	 Rx_mac_empty, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_err;
+   wire [31:0] 	 Tx_mac_data, Rx_mac_data;
+   wire [1:0] 	 Tx_mac_BE, Rx_mac_BE;
+   wire 	 rst_mac;
+  
+   oneshot_2clk mac_rst_1shot (.clk_in(wb_clk),.in(wb_rst),.clk_out(clk_to_mac),.out(rst_mac));
+   
+   MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11))
+     MAC_top
+       (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk),
+	.rst_mac(rst_mac),.rst_user(dsp_rst),
+	.RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]),
+	.WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack),
+	.Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE),
+	.Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
+	.Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
+	.Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
+	.Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),
+	.Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),
+	.Crs(GMII_CRS),.Col(GMII_COL),
+	.Mdio(MDIO),.Mdc(MDC),
+	.rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2),
+	.tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(),
+	.debug0(debug_mac0),.debug1(debug_mac1) );
+
+   assign 	 s6_err = 1'b0;
+   assign 	 s6_rty = 1'b0;
+
+   mac_rxfifo_int mac_rxfifo_int
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),
+      .Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop),
+      .Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
+      .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done),
+      .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full),
+      .fifo_occupied(eth_rx_occ),.fifo_full(eth_rx_full),.fifo_empty(eth_rx_empty) );
+
+   mac_txfifo_int mac_txfifo_int
+     (.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac),
+      .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
+      .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
+      .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done),
+      .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop),
+      .fifo_occupied(eth_tx_occ),.fifo_full(eth_tx_full),.fifo_empty(eth_tx_empty) );
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Interrupt Controller, Slave #8
+
+   wire [15:0] 	 irq={{4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
+		      {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
+   
+   simple_pic #(.is(16),.dwidth(32)) simple_pic
+     (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
+      .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
+      .irq(irq) );
+   assign 	 s8_err = 0;
+   assign 	 s8_rty = 0;
+ 	 
+   // /////////////////////////////////////////////////////////////////////////
+   // Master Timer, Slave #9
+
+   wire [31:0] 	 master_time;
+   timer timer
+     (.wb_clk_i(wb_clk),.rst_i(wb_rst),
+      .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
+      .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
+      .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
+   assign 	 s9_err = 0;
+   assign 	 s9_rty = 0;
+
+   // /////////////////////////////////////////////////////////////////////////
+   // UART, Slave #10
+
+   simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart  // depth of 3 is 128 entries
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack),
+      .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i),
+      .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
+      .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
+   
+   assign 	 s10_err = 0;
+   assign 	 s10_rty = 0;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // ATR Controller, Slave #11
+
+   wire 	 run_rx, run_tx;
+   reg 		 run_rx_d1;
+   always @(posedge dsp_clk)
+     run_rx_d1 <= run_rx;
+   
+   atr_controller atr_controller
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i),
+      .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack),
+      .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
+   assign 	 s11_err = 0;
+   assign 	 s11_rty = 0;
+   
+   // //////////////////////////////////////////////////////////////////////////
+   // Time Sync, Slave #12 
+
+   reg 		 pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1;
+   always @(negedge dsp_clk) pps_negedge <= pps_in;
+   always @(posedge dsp_clk) pps_posedge <= pps_in;
+   always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge;
+   always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge;   
+   
+   wire 	 pps_o;
+   time_sync time_sync
+     (.wb_clk_i(wb_clk),.rst_i(wb_rst),
+      .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]),
+      .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack),
+      .sys_clk_i(dsp_clk),.master_time_o(master_time),
+      .pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
+      .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
+      .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
+   assign 	 s12_err = 0;
+   assign 	 s12_rty = 0;
+
+   // /////////////////////////////////////////////////////////////////////////
+   // SD Card Reader / Writer, Slave #13
+
+   sd_spi_wb sd_spi_wb
+     (.clk(wb_clk),.rst(wb_rst),
+      .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
+      .wb_cyc_i(s13_cyc),.wb_stb_i(s13_stb),.wb_we_i(s13_we),
+      .wb_adr_i(s13_adr[3:2]),.wb_dat_i(s13_dat_o),.wb_dat_o(s13_dat_i),
+      .wb_ack_o(s13_ack) );
+   assign 	 s13_err = 0;
+   assign 	 s13_rty = 0;
+   // /////////////////////////////////////////////////////////////////////////
+   // DSP
+   wire [31:0] 	 sample_rx, sample_tx;
+   wire 	 strobe_rx, strobe_tx;
+
+   rx_control #(.FIFOSIZE(10)) rx_control
+     (.clk(dsp_clk), .rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .master_time(master_time),.overrun(overrun),
+      .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), .wr_error_o(wr1_error),
+      .wr_ready_i(wr1_ready), .wr_full_i(wr1_full),
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
+      .debug_rx(debug_rx) );
+   
+   // dummy_rx dsp_core_rx
+   dsp_core_rx dsp_core_rx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .io_rx(io_rx),.sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
+      .debug(debug_rx_dsp) );
+
+   tx_control #(.FIFOSIZE(10)) tx_control
+     (.clk(dsp_clk), .rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .master_time(master_time),.underrun(underrun),
+      .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop),
+      .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error),
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+      .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty),
+      .debug(debug_txc) );
+   
+   dsp_core_tx dsp_core_tx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .dac_a(dac_a),.dac_b(dac_b),
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) );
+
+   assign dsp_rst = wb_rst;
+
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // SERDES
+
+   serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+      .rd_dat_i(rd0_dat),.rd_read_o(rd0_read),.rd_done_o(rd0_done),.rd_error_o(rd0_error),
+      .rd_sop_i(rd0_sop),.rd_eop_i(rd0_eop),
+      .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+      .wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error),
+      .wr_ready_i(wr0_ready),.wr_full_i(wr0_full),
+      .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
+      .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
+      .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
+
+`ifdef EXTRAM
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // External RAM Interface
+
+   localparam PAGE_SIZE = 10;  // PAGE SIZE is in bytes, 10 = 1024 bytes
+
+   wire [15:0] bus2ram, ram2bus;
+   wire [15:0] bridge_adr;
+   wire [1:0]  bridge_sel;
+   wire        bridge_stb, bridge_cyc, bridge_we, bridge_ack;
+   
+   wire [19:0] page;
+   wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]};
+   setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				       .in(set_data),.out(page),.changed());
+
+   wb_bridge_16_32 bridge
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),
+      .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel),
+      .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack),
+      .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel),
+      .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack));
+
+   wb_zbt16_b wb_zbt16_b
+     (.clk(wb_clk),.rst(wb_rst),
+      .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel),
+      .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we),
+      .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn),
+      .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
+      .sram_mode(),.sram_zz() );
+
+   assign      s14_err = 0; assign s14_rty = 0;
+   assign      RAM_CE1n = 0;
+   assign      RAM_D[17:16] = 2'bzz;
+`endif
+
+`ifdef DEBUG   
+   // /////////////////////////////////////////////////////////////////////////////////////////
+   // Debug Pins
+   
+   // FIFO Level Debugging
+   reg [31:0]  host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo;
+   
+   always @(posedge dsp_clk)
+     serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]},
+			     {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
+
+   always @(posedge dsp_clk)
+     dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]},
+			     {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+   
+   always @(posedge dsp_clk)
+     host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]},
+			   {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
+   
+   always @(posedge dsp_clk)
+     dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]},
+			   {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+   
+   always @(posedge dsp_clk)
+     eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]},
+			{eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
+   
+   assign      debug_clk[0] = 0;
+   assign      debug_clk[1] = dsp_clk;	
+   
+   assign     debug = host_to_dsp_fifo; // debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
+   assign      debug_gpio_0 = eth_mac_debug;
+   assign      debug_gpio_1 = 0;
+`endif
+   
+endmodule // u2_core
+
+//   wire        debug_mux;
+//   setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+//					.in(set_data),.out(debug_mux),.changed());
+
+//assign     debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
+//assign     debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo;
+   
+//assign      debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
+//		{run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
+
+//assign      debug = debug_tx_dsp;
+//assign      debug = debug_serdes0;
+
+//assign      debug_gpio_0 = 0; //debug_serdes0;
+//assign      debug_gpio_1 = 0; //debug_serdes1;
+
+//   assign      debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success},
+//	      {8'b0},
+//      {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done },
+//    {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} };
+
+//assign      debug = {dac_a,dac_b};
+
+/*
+ assign      debug = {{ram_loader_done, takeover, 6'd0},
+ {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi},
+ {8'd0},
+ {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */
+
+/*assign      debug = host_to_dsp_fifo;
+ assign      debug_gpio_0 = eth_mac_debug;
+ assign      debug_gpio_1 = 0;
+ */
+// Assign various commonly used debug buses.
+/*
+ wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
+ irq[7:0],
+ GMII_RXD,
+ GMII_TXD};
+ 
+ wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
+   
+   wire [31:0] debug_time =  {uart_tx_o, 7'b0,
+			      irq[7:0],
+			      6'b0, GMII_RX_DV, GMII_TX_EN,
+			      4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int};
+
+   wire [31:0] debug_irq =  {uart_tx_o, iwb_adr, iwb_ack,
+			     irq[7:0],
+			     proc_int,  7'b0 };
+
+   wire [31:0] debug_eth = 
+	       {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
+		{8'd0},
+		{8'd0},
+		{GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} };
+
+   assign      debug_serdes0 = { { rd0_dat[7:0] },
+				 { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done },
+				 { ser_t[15:8] },
+				 { ser_t[7:0] } };
+
+   assign      debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write},
+				 { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en },
+				 { ser_r[15:8] },
+				 { ser_r[7:0] } };
+       
+   assign      debug_gpio_1 = {uart_tx_o,7'd0,
+			       3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error,
+			       debug_txc[15:0]};
+   assign      debug_gpio_1 = debug_rx;
+   assign      debug_gpio_1 = debug_serdes1;
+   assign      debug_gpio_1 = debug_eth;
+      
+    */
+      
diff --git a/usrp2/top/u2_rev3_2rx_iad/wave.sh b/usrp2/top/u2_rev3_2rx_iad/wave.sh
new file mode 100755
index 000000000..626f224e5
--- /dev/null
+++ b/usrp2/top/u2_rev3_2rx_iad/wave.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+gtkwave dsp_core_tb.vcd dsp_core_tb.sav &
diff --git a/usrp2/top/u2_rev3_iad/.gitignore b/usrp2/top/u2_rev3_iad/.gitignore
new file mode 100644
index 000000000..e4daaf1ea
--- /dev/null
+++ b/usrp2/top/u2_rev3_iad/.gitignore
@@ -0,0 +1,4 @@
+/build
+/*.vcd
+/dsp_core_tb
+/*.dat
diff --git a/usrp2/top/u2_rev3_iad/Makefile b/usrp2/top/u2_rev3_iad/Makefile
new file mode 100644
index 000000000..5ae8846dd
--- /dev/null
+++ b/usrp2/top/u2_rev3_iad/Makefile
@@ -0,0 +1,254 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u2_rev3
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family Spartan3 \
+device xc3s2000 \
+package fg456 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/buffer_int.v \
+control_lib/buffer_pool.v \
+control_lib/cascadefifo2.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/fifo_2clock.v \
+control_lib/fifo_2clock_casc.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/longfifo.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+eth/mac_rxfifo_int.v \
+eth/mac_txfifo_int.v \
+eth/rtl/verilog/Clk_ctrl.v \
+eth/rtl/verilog/MAC_rx.v \
+eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
+eth/rtl/verilog/MAC_rx/CRC_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
+eth/rtl/verilog/MAC_top.v \
+eth/rtl/verilog/MAC_tx.v \
+eth/rtl/verilog/MAC_tx/CRC_gen.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
+eth/rtl/verilog/MAC_tx/Random_gen.v \
+eth/rtl/verilog/Phy_int.v \
+eth/rtl/verilog/RMON.v \
+eth/rtl/verilog/RMON/RMON_addr_gen.v \
+eth/rtl/verilog/RMON/RMON_ctrl.v \
+eth/rtl/verilog/Reg_int.v \
+eth/rtl/verilog/eth_miim.v \
+eth/rtl/verilog/flow_ctrl_rx.v \
+eth/rtl/verilog/flow_ctrl_tx.v \
+eth/rtl/verilog/miim/eth_clockgen.v \
+eth/rtl/verilog/miim/eth_outputcontrol.v \
+eth/rtl/verilog/miim/eth_shiftreg.v \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/integrate.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u2_rev3/u2_rev3.ucf \
+top/u2_rev3/u2_rev3.v \
+top/u2_rev3_iad/dsp_core_rx.v
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High 
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+	@echo make proj, check, synth, bin, testbench, or clean
+
+proj:
+	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
+
+check:
+	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
+
+synth:
+	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
+
+bin:
+	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
+
+testbench:
+	iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v
+
+clean:
+	rm -rf $(BUILD_DIR)
+	rm -f dsp_core_tb
+	rm -f *.lx2
+	rm -f *.dat
+	rm -f *.vcd
diff --git a/usrp2/top/u2_rev3_iad/cmdfile b/usrp2/top/u2_rev3_iad/cmdfile
new file mode 100644
index 000000000..34373a676
--- /dev/null
+++ b/usrp2/top/u2_rev3_iad/cmdfile
@@ -0,0 +1,4 @@
+-y .
+-y ../../sdr_lib
+-y ../../control_lib
+-y ../../models
diff --git a/usrp2/top/u2_rev3_iad/dsp_core_rx.v b/usrp2/top/u2_rev3_iad/dsp_core_rx.v
new file mode 100644
index 000000000..2882464ba
--- /dev/null
+++ b/usrp2/top/u2_rev3_iad/dsp_core_rx.v
@@ -0,0 +1,158 @@
+`define DSP_CORE_RX_BASE 160
+module dsp_core_rx
+  (input clk, input rst,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   input [13:0] adc_a, input adc_ovf_a,
+   input [13:0] adc_b, input adc_ovf_b,
+   
+   input [15:0] io_rx,
+
+   output [31:0] sample,
+   input run,
+   output strobe,
+   output [31:0] debug
+   );
+
+   wire [15:0] scale_i, scale_q;
+   wire [13:0] adc_a_ofs, adc_b_ofs;
+   reg [13:0] adc_i, adc_q;
+   wire [31:0] phase_inc;
+   reg [31:0]  phase;
+
+   wire [35:0] prod_i, prod_q;
+   wire [23:0] i_cordic, q_cordic;
+   wire [31:0] i_iad, q_iad;
+   wire [15:0] i_out, q_out;
+   
+   wire        enable_hb1, enable_hb2; // Correspond to std firmware settings
+   wire [7:0]  cic_decim;              // for combined CIC/HB decimator
+   wire [9:0]  decim_rate;             // Reconstructed original decimation setting
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_inc),.changed());
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({scale_i,scale_q}),.changed());
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed());
+
+   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_a),.adc_out(adc_a_ofs));
+   
+   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_b),.adc_out(adc_b_ofs));
+
+   wire [3:0]  muxctrl;
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(muxctrl),.changed());
+
+   wire [1:0] gpio_ena;
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(gpio_ena),.changed());
+
+   // The TVRX connects to what is called adc_b, thus A and B are
+   // swapped throughout the design.
+   //
+   // In the interest of expediency and keeping the s/w sane, we just remap them here.
+   // The I & Q fields are mapped the same:
+   // 0 -> "the real A" (as determined by the TVRX)
+   // 1 -> "the real B"
+   // 2 -> const zero
+   
+   always @(posedge clk)
+     case(muxctrl[1:0])		// The I mapping
+       0: adc_i <= adc_b_ofs;	// "the real A"
+       1: adc_i <= adc_a_ofs;
+       2: adc_i <= 0;
+       default: adc_i <= 0;
+     endcase // case(muxctrl[1:0])
+          
+   always @(posedge clk)
+     case(muxctrl[3:2])		// The Q mapping
+       0: adc_q <= adc_b_ofs;	// "the real A"
+       1: adc_q <= adc_a_ofs;
+       2: adc_q <= 0;
+       default: adc_q <= 0;
+     endcase // case(muxctrl[3:2])
+       
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(~run)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+
+   MULT18X18S mult_i
+     (.P(prod_i),    // 36-bit multiplier output
+      .A({{4{adc_i[13]}},adc_i} ),    // 18-bit multiplier input
+      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      );
+
+   MULT18X18S mult_q
+     (.P(prod_q),    // 36-bit multiplier output
+      .A({{4{adc_q[13]}},adc_q} ),    // 18-bit multiplier input
+      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      ); 
+
+   
+   cordic_z24 #(.bitwidth(24))
+     cordic(.clock(clk), .reset(rst), .enable(run),
+	    .xi(prod_i[24:1]),. yi(prod_q[24:1]), .zi(phase[31:8]),
+	    .xo(i_cordic),.yo(q_cordic),.zo() );
+
+   // Reconstruct original decimation rate from standard firmware settings
+   assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : 
+                                                  {1'b0,cic_decim,1'b0 }) :
+				    cic_decim;
+
+   cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator
+   cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate),
+	       .strobe_fast(1),.strobe_slow(strobe_iad) );
+
+   integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i
+     (.clk_i(clk),.rst_i(rst),.ena_i(run),
+      .dump_i(strobe_iad),.data_i(i_cordic),
+      .stb_o(strobe),.integ_o(i_iad) );
+
+   integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q
+     (.clk_i(clk),.rst_i(rst),.ena_i(run),
+      .dump_i(strobe_iad),.data_i(q_cordic),
+      .stb_o(),.integ_o(q_iad) );
+   
+   round #(.bits_in(32),.bits_out(16)) round_iout (.in(i_iad),.out(i_out));
+   round #(.bits_in(32),.bits_out(16)) round_qout (.in(q_iad),.out(q_out));
+  
+   // Streaming GPIO
+   //
+   // io_rx[15] => I channel LSB if gpio_ena[0] high
+   // io_rx[14] => Q channel LSB if gpio_ena[1] high
+
+   reg [31:0] sample_reg;
+   always @(posedge clk)
+     begin
+	sample_reg[31:17] <= i_out[15:1];
+	sample_reg[15:1]  <= q_out[15:1];
+	sample_reg[16]    <= gpio_ena[0] ? io_rx[15] : i_out[0]; 
+	sample_reg[0]     <= gpio_ena[1] ? io_rx[14] : q_out[0];
+     end
+   
+   assign      sample = sample_reg;
+   assign      debug = {clk, rst, run, strobe};
+   
+endmodule // dsp_core_rx
diff --git a/usrp2/top/u2_rev3_iad/dsp_core_tb.sav b/usrp2/top/u2_rev3_iad/dsp_core_tb.sav
new file mode 100644
index 000000000..17c90cdd7
--- /dev/null
+++ b/usrp2/top/u2_rev3_iad/dsp_core_tb.sav
@@ -0,0 +1,61 @@
+[size] 1680 975
+[pos] -1 -1
+*-24.007835 13660000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] dsp_core_tb.
+@200
+-SYSCON
+@28
+dsp_core_tb.clk
+dsp_core_tb.rst
+dsp_core_tb.run
+@200
+-
+-Settings Bus
+@22
+dsp_core_tb.set_addr[7:0]
+@24
+dsp_core_tb.set_data[31:0]
+@28
+dsp_core_tb.set_stb
+@200
+-
+-RX DSP CORE
+-
+@24
+dsp_core_tb.rx_path.decim_rate[9:0]
+@200
+-
+@8420
+dsp_core_tb.adc_a[13:0]
+@20000
+-
+@200
+-
+@8420
+dsp_core_tb.rx_path.adc_a_ofs[13:0]
+@20000
+-
+@200
+-
+@8022
+dsp_core_tb.rx_path.i_cordic[23:0]
+@20000
+-
+@200
+-
+@8022
+dsp_core_tb.rx_path.i_iad[31:0]
+@20000
+-
+@200
+-
+@8420
+dsp_core_tb.rx_path.i_out[15:0]
+@20000
+-
+@200
+-
+@28
+dsp_core_tb.stb
+@200
+-
diff --git a/usrp2/top/u2_rev3_iad/dsp_core_tb.v b/usrp2/top/u2_rev3_iad/dsp_core_tb.v
new file mode 100644
index 000000000..4d5a5b537
--- /dev/null
+++ b/usrp2/top/u2_rev3_iad/dsp_core_tb.v
@@ -0,0 +1,196 @@
+`timescale 1ns / 100ps
+
+module dsp_core_tb;
+
+///////////////////////////////////////////////////////////////////////////////////
+// Sim-wide wires/busses                                                         //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   // System control bus
+   reg                clk = 0;
+   reg                rst = 1;
+   
+   // Configuration bus
+   reg                set_stb = 0;  
+   reg          [7:0] set_addr = 0; 
+   reg         [31:0] set_data = 0; 
+
+   // ADC input bus
+   wire signed [13:0] adc_a;
+   wire signed [13:0] adc_b;
+   wire               adc_ovf_a;
+   wire               adc_ovf_b;
+   
+   // RX sample bus
+   reg                run = 1;
+   wire        [31:0] sample;
+   wire               stb;
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Simulation control                                                            //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   // Set up output files
+   initial begin
+      $dumpfile("dsp_core_tb.vcd");
+      $dumpvars(0,dsp_core_tb);
+   end
+
+   // Update display every 10 us
+   always #1000 $monitor("Time in us ",$time/1000);
+
+   // Generate master clock 50% @ 100 MHz
+   always
+     #5 clk = ~clk;
+
+///////////////////////////////////////////////////////////////////////////////////
+// Unit(s) under test                                                            //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   reg [13:0] amplitude = 13'h1fff;
+   reg [15:0] impulse_len = 0;
+   reg [15:0] zero_len = 0;
+   reg 	      adc_ena = 0;
+
+   initial #500 @(posedge clk) adc_ena = 1;
+
+   impulse adc
+     (.clk(clk),.rst(rst),.ena(adc_ena),
+      .dc_offset_a(0),.dc_offset_b(0),
+      .amplitude(amplitude),
+      .impulse_len(impulse_len),.zero_len(zero_len),
+      .adc_a(adc_a),.adc_b(adc_b),
+      .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) );
+
+   initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's
+   initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset
+   dsp_core_rx rx_path
+     (.clk(clk),.rst(rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),
+      .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .io_rx(16'b0),
+      .run(adc_ena),.sample(sample),.strobe(stb),
+      .debug() );
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Simulation output/checking                                                    //
+///////////////////////////////////////////////////////////////////////////////////
+
+   integer rx_file;
+   
+   initial
+     rx_file = $fopen("rx.dat", "wb");
+   
+   always @(posedge clk)
+     begin
+	// Write RX sample I&Q in format Octave can load
+	if (stb)
+	  begin
+	     $fwrite(rx_file, sample[31:16]);
+	     $fputc(32, rx_file);
+	     $fwrite(rx_file, sample[15:0]);
+	     $fputc(13, rx_file);
+	  end
+     end
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Tasks                                                                         //
+///////////////////////////////////////////////////////////////////////////////////
+
+   task power_on;
+     begin
+	@(posedge clk)
+	  rst = #1 1'b1;
+	@(posedge clk)
+	  rst = #1 1'b0;
+     end
+   endtask // power_on
+   
+   task set_impulse_len;
+      input [15:0] len;
+      @(posedge clk) impulse_len = len-1;
+   endtask
+ 
+   task set_zero_len;
+      input [15:0] len;
+      @(posedge clk) zero_len = len-1;
+   endtask
+
+   // Strobe configuration bus with addr, data
+   task write_cfg_register;
+      input [7:0]  regno;
+      input [31:0] value;
+      
+      begin
+	 @(posedge clk);
+	 set_addr <= regno;
+	 set_data <= value;
+	 set_stb  <= 1'b1;
+	 @(posedge clk);
+	 set_stb  <= 1'b0;
+      end
+   endtask // write_cfg_register
+
+   // Set RX DDC frequency
+   task set_ddc_freq;
+      input [31:0] freq;
+
+      write_cfg_register(160, freq);
+   endtask // set_ddc_freq
+
+   // Set RX IQ scaling registers
+   task set_rx_scale_iq;
+      input [15:0] scale_i;
+      input [15:0] scale_q;
+
+      write_cfg_register(161, {scale_i,scale_q});
+   endtask // set_rx_scale_iq
+   
+   // Set RX MUX control
+   task set_rx_muxctrl;
+      input [3:0] muxctrl;
+
+      write_cfg_register(168, muxctrl);
+   endtask // set_rx_muxctrl
+   
+   // Set RX CIC decim and halfband enables
+   task set_decim;
+      input hb1_ena;
+      input hb2_ena;
+      input [7:0] decim;
+
+      write_cfg_register(162, {hb1_ena,hb2_ena,decim});
+   endtask // set_decim
+      
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Individual tests                                                              //
+///////////////////////////////////////////////////////////////////////////////////
+
+   task test_rx;
+      begin
+	 set_impulse_len(1);
+	 set_zero_len(999);
+	 set_rx_muxctrl(1);
+	 set_ddc_freq(0);
+	 set_rx_scale_iq(1243, 1243);
+	 set_decim(0, 1, 3);
+
+	 #100000 $finish;
+      end
+   endtask // test_rx
+   
+      
+///////////////////////////////////////////////////////////////////////////////////
+// Top-level test                                                                //
+///////////////////////////////////////////////////////////////////////////////////
+
+   // Execute tests
+   initial
+     begin
+	power_on();
+	test_rx();
+     end
+
+endmodule // dsp_core_tb
diff --git a/usrp2/top/u2_rev3_iad/impulse.v b/usrp2/top/u2_rev3_iad/impulse.v
new file mode 100644
index 000000000..7f0cdc9be
--- /dev/null
+++ b/usrp2/top/u2_rev3_iad/impulse.v
@@ -0,0 +1,63 @@
+module impulse
+  (input clk,
+   input rst,
+   input ena,
+   
+   input [13:0] dc_offset_a,
+   input [13:0] dc_offset_b,
+   input [13:0] amplitude,
+   input [15:0] impulse_len,
+   input [15:0] zero_len,
+
+   output [13:0] adc_a,
+   output [13:0] adc_b,
+   output        adc_ovf_a,
+   output        adc_ovf_b
+   );
+
+   reg [13:0] adc_a_int = 0;
+   reg [15:0] count;
+
+   localparam ST_ZERO = 0;
+   localparam ST_HIGH = 1;
+   reg 	      state;
+   
+   always @(posedge clk)
+     if (rst | ~ena)
+       begin
+	  adc_a_int <= 0;
+	  count <= 0;
+	  state <= ST_ZERO;
+       end
+     else
+       case(state)
+	 ST_ZERO:
+	   if (count == zero_len)
+	     begin
+		adc_a_int <= amplitude;
+		state <= ST_HIGH;
+		count <= 0;
+	     end
+	   else
+	     count <= count + 1;
+
+	 ST_HIGH:
+	   if (count == impulse_len)
+	     begin
+		adc_a_int <= 0;
+		state <= ST_ZERO;
+		count <= 0;
+	     end
+	   else
+	     count <= count + 1;
+
+       endcase // case (state)
+
+   assign adc_a = adc_a_int + dc_offset_a;
+
+   // Ignore for now
+   assign adc_b = dc_offset_b;
+   assign adc_ovf_a = 0;
+   assign adc_ovf_b = 0;
+
+endmodule // impulse
diff --git a/usrp2/top/u2_rev3_iad/wave.sh b/usrp2/top/u2_rev3_iad/wave.sh
new file mode 100755
index 000000000..626f224e5
--- /dev/null
+++ b/usrp2/top/u2_rev3_iad/wave.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+gtkwave dsp_core_tb.vcd dsp_core_tb.sav &
diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf
new file mode 100755
index 000000000..091eb2005
--- /dev/null
+++ b/usrp2/top/u2plus/u2plus.ucf
@@ -0,0 +1,354 @@
+NET "DAC_LOCK"  LOC = "P4"  ;
+NET "ADC_clkout_p"  LOC = "P1"  ;
+NET "ADC_clkout_n"  LOC = "P2"  ;
+NET "io_rx<15>"  LOC = "AD1"  ;
+NET "io_rx<14>"  LOC = "AD2"  ;
+NET "io_rx<13>"  LOC = "AC2"  ;
+NET "io_rx<12>"  LOC = "AC3"  ;
+NET "io_rx<11>"  LOC = "W7"  ;
+NET "io_rx<10>"  LOC = "W6"  ;
+NET "io_rx<09>"  LOC = "U9"  ;
+NET "io_rx<08>"  LOC = "V8"  ;
+NET "io_rx<07>"  LOC = "AB1"  ;
+NET "io_rx<06>"  LOC = "AC1"  ;
+NET "io_rx<05>"  LOC = "V7"  ;
+NET "io_rx<04>"  LOC = "V6"  ;
+NET "io_rx<03>"  LOC = "Y5"  ;
+NET "ADCB_2_3_p"  LOC = "U7"  ;
+NET "ADCB_2_3_n"  LOC = "U8"  ;
+NET "ADCB_0_1_p"  LOC = "AA2"  ;
+NET "ADCB_0_1_n"  LOC = "AA3"  ;
+NET "ADCA_12_13_p"  LOC = "Y1"  ;
+NET "ADCA_12_13_n"  LOC = "Y2"  ;
+NET "ADCA_10_11_p"  LOC = "W3"  ;
+NET "ADCA_10_11_n"  LOC = "W4"  ;
+NET "ADCA_8_9_p"  LOC = "T7"  ;
+NET "ADCA_8_9_n"  LOC = "U6"  ;
+NET "ADCA_6_7_p"  LOC = "U5"  ;
+NET "ADCA_6_7_n"  LOC = "V5"  ;
+NET "ADCA_4_5_p"  LOC = "T10"  ;
+NET "ADCA_4_5_n"  LOC = "T9"  ;
+NET "ADCA_2_3_p"  LOC = "V1"  ;
+NET "ADCA_2_3_n"  LOC = "V2"  ;
+NET "ADCA_0_1_p"  LOC = "R8"  ;
+NET "ADCA_0_1_n"  LOC = "R7"  ;
+NET "TX00_A"  LOC = "P8"  ;
+NET "TX01_A"  LOC = "P9"  ;
+NET "TX02_A"  LOC = "R5"  ;
+NET "TX03_A"  LOC = "R6"  ;
+NET "TX04_A"  LOC = "P7"  ;
+NET "TX05_A"  LOC = "P6"  ;
+NET "TX06_A"  LOC = "T3"  ;
+NET "TX07_A"  LOC = "T4"  ;
+NET "TX08_A"  LOC = "R3"  ;
+NET "TX09_A"  LOC = "R4"  ;
+NET "TX10_A"  LOC = "R2"  ;
+NET "TX11_A"  LOC = "N1"  ;
+NET "TX12_A"  LOC = "N2"  ;
+NET "TX13_A"  LOC = "N5"  ;
+NET "TX14_A"  LOC = "N4"  ;
+NET "TX15_A"  LOC = "M2"  ;
+NET "TX00_B"  LOC = "M5"  ;
+NET "TX01_B"  LOC = "M6"  ;
+NET "TX02_B"  LOC = "M4"  ;
+NET "TX03_B"  LOC = "M3"  ;
+NET "TX04_B"  LOC = "M8"  ;
+NET "TX05_B"  LOC = "M7"  ;
+NET "TX06_B"  LOC = "L4"  ;
+NET "TX07_B"  LOC = "L3"  ;
+NET "TX08_B"  LOC = "K3"  ;
+NET "TX09_B"  LOC = "K2"  ;
+NET "TX10_B"  LOC = "K5"  ;
+NET "TX11_B"  LOC = "K4"  ;
+NET "TX12_B"  LOC = "M10"  ;
+NET "TX13_B"  LOC = "M9"  ;
+NET "TX14_B"  LOC = "J5"  ;
+NET "TX15_B"  LOC = "J4"  ;
+NET "io_tx<15>"  LOC = "K6"  ;
+NET "io_tx<14>"  LOC = "L7"  ;
+NET "io_tx<13>"  LOC = "H2"  ;
+NET "io_tx<12>"  LOC = "H1"  ;
+NET "io_tx<11>"  LOC = "L10"  ;
+NET "io_tx<10>"  LOC = "L9"  ;
+NET "io_tx<09>"  LOC = "G3"  ;
+NET "io_tx<08>"  LOC = "F3"  ;
+NET "io_tx<07>"  LOC = "K7"  ;
+NET "io_tx<06>"  LOC = "J6"  ;
+NET "io_tx<05>"  LOC = "E1"  ;
+NET "io_tx<04>"  LOC = "F2"  ;
+NET "io_tx<03>"  LOC = "J7"  ;
+NET "io_tx<02>"  LOC = "H6"  ;
+NET "io_tx<01>"  LOC = "F5"  ;
+NET "io_tx<00>"  LOC = "G4"  ;
+NET "MOSI_RX_ADC"  LOC = "E3"  ;
+NET "SCLK_RX_ADC"  LOC = "F4"  ;
+NET "SEN_RX_ADC"  LOC = "D3"  ;
+NET "SCLK_RX_DAC"  LOC = "E4"  ;
+NET "SEN_RX_DAC"  LOC = "K9"  ;
+NET "MOSI_RX_DAC"  LOC = "K8"  ;
+NET "SCLK_RX_DB"  LOC = "G6"  ;
+NET "MOSI_RX_DB"  LOC = "H7"  ;
+NET "SEN_RX_DB"  LOC = "B2"  ;
+NET "SCLK_ADC"  LOC = "B1"  ;
+NET "MOSI_ADC"  LOC = "J8"  ;
+NET "SEN_ADC"  LOC = "J9"  ;
+NET "ADCB_4_5_p"  LOC = "AE1"  ;
+NET "ADCB_4_5_n"  LOC = "AE2"  ;
+NET "ADCB_6_7_p"  LOC = "W1"  ;
+NET "ADCB_6_7_n"  LOC = "W2"  ;
+NET "ADCB_8_9_p"  LOC = "U3"  ;
+NET "ADCB_8_9_n"  LOC = "V4"  ;
+NET "ADCB_10_11_p"  LOC = "J1"  ;
+NET "ADCB_10_11_n"  LOC = "K1"  ;
+NET "ADCB_12_13_p"  LOC = "J3"  ;
+NET "ADCB_12_13_n"  LOC = "J2"  ;
+NET "MISO_RX_DB"  LOC = "H4"  ;
+NET "MISO_RX_ADC"  LOC = "C1"  ;
+NET "MISO_TX_DB"  LOC = "AA5"  ;
+NET "MISO_DAC"  LOC = "Y3"  ;
+NET "MISO_TX_ADC"  LOC = "G1"  ;
+NET "io_rx<02>"  LOC = "R10"  ;
+NET "io_rx<01>"  LOC = "R1"  ;
+NET "io_rx<00>"  LOC = "M1"  ;
+NET "exp_user_out_p"  LOC = "AF14"  ;
+NET "exp_user_out_n"  LOC = "AE14"  ;
+NET "exp_time_out_p"  LOC = "Y14"  ;
+NET "exp_time_out_n"  LOC = "AA14"  ;
+NET "CLK_FPGA_P"  LOC = "AA13"  ;
+NET "CLK_FPGA_N"  LOC = "Y13"  ;
+NET "leds<5>"  LOC = "AF25"  ;
+NET "leds<4>"  LOC = "AE25"  ;
+NET "leds<3>"  LOC = "AF23"  ;
+NET "leds<2>"  LOC = "AE23"  ;
+NET "leds<1>"  LOC = "AB18"  ;
+NET "SEN_CLK"  LOC = "AA18"  ;
+NET "MOSI_CLK"  LOC = "W17"  ;
+NET "SCLK_CLK"  LOC = "V17"  ;
+NET "CLK_STATUS"  LOC = "AD22"  ;
+NET "CLK_FUNC"  LOC = "AC21"  ;
+NET "clk_sel<0>"  LOC = "AE21"  ;
+NET "clk_sel<1>"  LOC = "AD21"  ;
+NET "clk_en<1>"  LOC = "AA17"  ;
+NET "clk_en<0>"  LOC = "Y17"  ;
+NET "SDA"  LOC = "V16"  ;
+NET "SCL"  LOC = "U16"  ;
+NET "TXD3"  LOC = "AD20"  ;
+NET "TXD2"  LOC = "AC20"  ;
+NET "TXD1"  LOC = "AD19"  ;
+NET "debug<00>"  LOC = "AC19"  ;
+NET "debug<01>"  LOC = "AF20"  ;
+NET "debug<02>"  LOC = "AE20"  ;
+NET "debug<03>"  LOC = "AC16"  ;
+NET "debug<04>"  LOC = "AB16"  ;
+NET "debug<05>"  LOC = "AF19"  ;
+NET "debug<06>"  LOC = "AE19"  ;
+NET "debug<07>"  LOC = "V15"  ;
+NET "debug<08>"  LOC = "U15"  ;
+NET "debug<09>"  LOC = "AE17"  ;
+NET "debug<10>"  LOC = "AD17"  ;
+NET "debug<11>"  LOC = "V14"  ;
+NET "debug<12>"  LOC = "W15"  ;
+NET "debug<13>"  LOC = "AC15"  ;
+NET "debug<14>"  LOC = "AD14"  ;
+NET "debug<15>"  LOC = "AC14"  ;
+NET "debug_clk<1>"  LOC = "AD11"  ;
+NET "debug<16>"  LOC = "AC11"  ;
+NET "debug<17>"  LOC = "AB12"  ;
+NET "debug<18>"  LOC = "AC12"  ;
+NET "debug<19>"  LOC = "V13"  ;
+NET "debug<20>"  LOC = "W13"  ;
+NET "debug<21>"  LOC = "AE8"  ;
+NET "debug<22>"  LOC = "AF8"  ;
+NET "debug<23>"  LOC = "V12"  ;
+NET "debug<24>"  LOC = "W12"  ;
+NET "debug<25>"  LOC = "AB9"  ;
+NET "debug<26>"  LOC = "AC9"  ;
+NET "debug<27>"  LOC = "AC8"  ;
+NET "debug<28>"  LOC = "AB7"  ;
+NET "debug<29>"  LOC = "V11"  ;
+NET "debug<30>"  LOC = "U11"  ;
+NET "debug<31>"  LOC = "Y10"  ;
+NET "debug_clk<0>"  LOC = "AA10"  ;
+NET "SEN_DAC"  LOC = "AE7"  ;
+NET "SCLK_DAC"  LOC = "AF5"  ;
+NET "MOSI_DAC"  LOC = "AE6"  ;
+NET "MOSI_TX_ADC"  LOC = "V10"  ;
+NET "SEN_TX_ADC"  LOC = "W10"  ;
+NET "SCLK_TX_ADC"  LOC = "AC6"  ;
+NET "MOSI_TX_DAC"  LOC = "AD6"  ;
+NET "SEN_TX_DAC"  LOC = "AE4"  ;
+NET "SCLK_TX_DAC"  LOC = "AF4"  ;
+NET "SCLK_TX_DB"  LOC = "AE3"  ;
+NET "MOSI_TX_DB"  LOC = "AF3"  ;
+NET "SEN_TX_DB"  LOC = "W9"  ;
+NET "RXD3"  LOC = "AF17"  ;
+NET "RXD2"  LOC = "AF15"  ;
+NET "RXD1"  LOC = "AD12"  ;
+NET "MISO_CLK"  LOC = "AC10"  ;
+NET "PPS_IN"  LOC = "AB6"  ;
+NET "PPS2_IN"  LOC = "AA20"  ;
+NET "ser_rx_clk"  LOC = "P18"  ;
+NET "ser_tx_clk"  LOC = "P23"  ;   # SERDES TX CLK
+NET "CLK_TO_MAC"  LOC = "P26"  ;
+NET "GMII_TX_CLK"  LOC = "P25"  ;
+NET "GMII_RX_CLK"  LOC = "P21"  ;
+NET "ETH_LED"  LOC = "H20"  ;
+NET "GMII_TXD7"  LOC = "G21"  ;
+NET "GMII_TXD6"  LOC = "C26"  ;
+NET "GMII_TXD5"  LOC = "C25"  ;
+NET "GMII_TXD4"  LOC = "J21"  ;
+NET "GMII_TXD3"  LOC = "H21"  ;
+NET "GMII_TXD2"  LOC = "D25"  ;
+NET "GMII_TXD1"  LOC = "D24"  ;
+NET "GMII_TXD0"  LOC = "E26"  ;
+NET "GMII_TX_EN"  LOC = "D26"  ;
+NET "GMII_TX_ER"  LOC = "J19"  ;
+NET "GMII_GTX_CLK"  LOC = "J20"  ;
+NET "GMII_RXD7"  LOC = "G22"  ;
+NET "GMII_RXD6"  LOC = "K19"  ;
+NET "GMII_RXD5"  LOC = "K18"  ;
+NET "GMII_RXD4"  LOC = "E24"  ;
+NET "GMII_RXD3"  LOC = "F23"  ;
+NET "GMII_RXD2"  LOC = "L18"  ;
+NET "GMII_RXD1"  LOC = "L17"  ;
+NET "GMII_RXD0"  LOC = "F25"  ;
+NET "GMII_RX_DV"  LOC = "F24"  ;
+NET "GMII_RX_ER"  LOC = "L20"  ;
+NET "GMII_CRS"  LOC = "K20"  ;
+NET "GMII_COL"  LOC = "G23"  ;
+NET "PHY_INTn"  LOC = "L22"  ;
+NET "MDIO"  LOC = "K21"  ;
+NET "MDC"  LOC = "J23"  ;
+NET "PHY_RESET"  LOC = "J22"  ;
+NET "exp_time_in_p"  LOC = "N18"  ;
+NET "exp_time_in_n"  LOC = "N17"  ;
+NET "exp_user_in_p"  LOC = "L24"  ;
+NET "exp_user_in_n"  LOC = "M23"  ;
+NET "ser_prbsen"  LOC = "U23"  ;
+NET "ser_loopen"  LOC = "R19"  ;
+NET "ser_enable"  LOC = "R20"  ;
+NET "ser_t<15>"  LOC = "V23"  ;
+NET "ser_t<14>"  LOC = "U22"  ;
+NET "ser_t<13>"  LOC = "V24"  ;
+NET "ser_t<12>"  LOC = "V25"  ;
+NET "ser_t<11>"  LOC = "W23"  ;
+NET "ser_t<10>"  LOC = "V22"  ;
+NET "ser_t<09>"  LOC = "T18"  ;
+NET "ser_t<08>"  LOC = "T17"  ;
+NET "ser_t<07>"  LOC = "Y24"  ;
+NET "ser_t<06>"  LOC = "Y25"  ;
+NET "ser_t<05>"  LOC = "U21"  ;
+NET "ser_t<04>"  LOC = "T20"  ;
+NET "ser_t<03>"  LOC = "Y22"  ;
+NET "ser_t<02>"  LOC = "Y23"  ;
+NET "ser_t<01>"  LOC = "U19"  ;
+NET "ser_t<00>"  LOC = "U18"  ;
+NET "ser_tkmsb"  LOC = "AA24"  ;
+NET "ser_tklsb"  LOC = "AA25"  ;
+NET "ser_r<15>"  LOC = "V21"  ;
+NET "ser_r<14>"  LOC = "U20"  ;
+NET "ser_r<13>"  LOC = "AA22"  ;
+NET "ser_r<12>"  LOC = "AA23"  ;
+NET "ser_r<11>"  LOC = "V18"  ;
+NET "ser_r<10>"  LOC = "V19"  ;
+NET "ser_r<09>"  LOC = "AB23"  ;
+NET "ser_r<08>"  LOC = "AC26"  ;
+NET "ser_r<07>"  LOC = "AB26"  ;
+NET "ser_r<06>"  LOC = "AD26"  ;
+NET "ser_r<05>"  LOC = "AC25"  ;
+NET "ser_r<04>"  LOC = "W20"  ;
+NET "ser_r<03>"  LOC = "W21"  ;
+NET "ser_r<02>"  LOC = "AC23"  ;
+NET "ser_r<01>"  LOC = "AC24"  ;
+NET "ser_r<00>"  LOC = "AE26"  ;
+NET "ser_rkmsb"  LOC = "AD25"  ;
+NET "ser_rklsb"  LOC = "Y20"  ;
+NET "ser_rx_en"  LOC = "Y21"  ;
+NET "FPGA_RESET"  LOC = "K24"  ;
+NET "RAM_D<17>"  LOC = "F7"  ;
+NET "RAM_D<16>"  LOC = "E7"  ;
+NET "RAM_D<15>"  LOC = "G9"  ;
+NET "RAM_D<14>"  LOC = "H9"  ;
+NET "RAM_D<13>"  LOC = "G10"  ;
+NET "RAM_D<12>"  LOC = "H10"  ;
+NET "RAM_D<11>"  LOC = "A4"  ;
+NET "RAM_D<10>"  LOC = "B4"  ;
+NET "RAM_D<09>"  LOC = "C5"  ;
+NET "RAM_D<08>"  LOC = "D6"  ;
+NET "RAM_D<07>"  LOC = "J11"  ;
+NET "RAM_D<06>"  LOC = "K11"  ;
+NET "RAM_D<05>"  LOC = "B7"  ;
+NET "RAM_D<04>"  LOC = "C7"  ;
+NET "RAM_D<03>"  LOC = "B6"  ;
+NET "RAM_D<02>"  LOC = "C6"  ;
+NET "RAM_D<01>"  LOC = "C8"  ;
+NET "RAM_D<00>"  LOC = "D8"  ;
+NET "RAM_ZZ"  LOC = "J12"  ;
+NET "RAM_BWn<3>"  LOC = "D9"  ;
+NET "RAM_BWn<2>"  LOC = "A9"  ;
+NET "RAM_BWn<1>"  LOC = "B9"  ;
+NET "RAM_BWn<0>"  LOC = "G12"  ;
+NET "RAM_LDn"  LOC = "H12"  ;
+NET "RAM_OEn"  LOC = "C10"  ;
+NET "RAM_WEn"  LOC = "D10"  ;
+NET "RAM_CLK"  LOC = "A10"  ;
+NET "RAM_CENn"  LOC = "B10"  ;
+NET "RAM_A<00>"  LOC = "C11"  ;
+NET "RAM_A<01>"  LOC = "E12"  ;
+NET "RAM_A<02>"  LOC = "F12"  ;
+NET "RAM_A<03>"  LOC = "D13"  ;
+NET "RAM_A<04>"  LOC = "C12"  ;
+NET "RAM_A<05>"  LOC = "A12"  ;
+NET "RAM_A<06>"  LOC = "B12"  ;
+NET "RAM_A<07>"  LOC = "E14"  ;
+NET "RAM_A<08>"  LOC = "F14"  ;
+NET "RAM_A<09>"  LOC = "B15"  ;
+NET "RAM_A<10>"  LOC = "A15"  ;
+NET "RAM_A<11>"  LOC = "D16"  ;
+NET "RAM_A<12>"  LOC = "C15"  ;
+NET "RAM_A<13>"  LOC = "D17"  ;
+NET "RAM_A<14>"  LOC = "C16"  ;
+NET "RAM_A<15>"  LOC = "F15"  ;
+NET "RAM_A<16>"  LOC = "C17"  ;
+NET "RAM_A<17>"  LOC = "B17"  ;
+NET "RAM_A<18>"  LOC = "B18"  ;
+NET "RAM_A<19>"  LOC = "A18"  ;
+NET "RAM_A<20>"  LOC = "D18"  ;
+NET "RAM_D<35>"  LOC = "K16"  ;
+NET "RAM_D<34>"  LOC = "D20"  ;
+NET "RAM_D<33>"  LOC = "C20"  ;
+NET "RAM_D<32>"  LOC = "E21"  ;
+NET "RAM_D<31>"  LOC = "D21"  ;
+NET "RAM_D<30>"  LOC = "C21"  ;
+NET "RAM_D<29>"  LOC = "B21"  ;
+NET "RAM_D<28>"  LOC = "H17"  ;
+NET "RAM_D<27>"  LOC = "G17"  ;
+NET "RAM_D<26>"  LOC = "B23"  ;
+NET "RAM_D<25>"  LOC = "A22"  ;
+NET "RAM_D<24>"  LOC = "D23"  ;
+NET "RAM_D<23>"  LOC = "C23"  ;
+NET "RAM_D<22>"  LOC = "D22"  ;
+NET "RAM_D<21>"  LOC = "C22"  ;
+NET "RAM_D<20>"  LOC = "F19"  ;
+NET "RAM_D<19>"  LOC = "G20"  ;
+NET "RAM_D<18>"  LOC = "F20"  ;
+#NET "unnamed_net20"  LOC = "V20"  ;  # SUSPEND
+NET "PROG_B"  LOC = "A2"  ;
+NET "PUDC_B"  LOC = "G8"  ;
+NET "DONE"  LOC = "AB21"  ;
+NET "flash_miso"  LOC = "AF24"  ;
+NET "flash_clk"  LOC = "AE24"  ;
+NET "INIT_B"  LOC = "AA15"  ;
+NET "flash_mosi"  LOC = "AB15"  ;
+#NET "unnamed_net19"  LOC = "AE9"  ;    # VS1
+#NET "unnamed_net18"  LOC = "AF9"  ;    # VS0
+#NET "unnamed_net17"  LOC = "AA12"  ;   # VS2
+#NET "unnamed_net16"  LOC = "Y7"  ;     # M2
+NET "flash_cs"  LOC = "AA7"  ;
+#NET "unnamed_net15"  LOC = "AC4"  ;    # M1
+#NET "unnamed_net14"  LOC = "AD4"  ;    # M0
+#NET "unnamed_net13"  LOC = "D4"  ;     # TMS
+#NET "unnamed_net12"  LOC = "E23"  ;    # TDO
+#NET "unnamed_net11"  LOC = "G7"  ;     # TDI
+#NET "unnamed_net10"  LOC = "A25"  ;    # TCK
+
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v
new file mode 100644
index 000000000..e95445867
--- /dev/null
+++ b/usrp2/top/u2plus/u2plus.v
@@ -0,0 +1,377 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2plus
+  (
+   // Misc, debug
+   output [4:0] leds,  // LED4 is shared w/INIT_B
+   input [3:0] dipsw,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+   output uart_tx_o,
+   input uart_rx_i,
+   
+   // Expansion
+   input exp_pps_in_p, // Diff
+   input exp_pps_in_n, // Diff
+   output exp_pps_out_p, // Diff 
+   output exp_pps_out_n, // Diff 
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output reg [7:0] GMII_TXD,
+   output reg GMII_TX_EN,
+   output reg GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+   input PHY_CLK,   // possibly use on-board osc
+   input clk_to_mac,
+   output eth_led,
+   
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output reg [15:0] ser_t,
+   output reg ser_tklsb,
+   output reg ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_oen_a,
+   output adc_pdn_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_oen_b,
+   output adc_pdn_b,
+   
+   // DAC
+   output [15:0] dac_a,
+   output [15:0] dac_b,
+   input dac_lock,     // unused for now
+   
+   // I2C
+   inout SCL,
+   inout SDA,
+
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Clocks
+   input clk_fpga_p,  // Diff
+   input clk_fpga_n,  // Diff
+   input pps_in,
+   input POR,
+   
+   // AD9510 SPI
+   output sclk,
+   output sen_clk,
+   output sdi,
+   input sdo,
+
+   // TX side SPI -- tx_db, tx_adc, tx_dac, 9777
+   output sen_dac,
+   output sen_tx_db,
+   output sen_tx_adc,
+   output sen_tx_dac,
+   output mosi_tx,
+   input miso_dac,
+   input miso_tx_db,
+   input miso_tx_adc,
+   output sclk_tx,
+
+   // RX side SPI
+   output sen_rx_db,
+   output sclk_rx_db,
+   input sdo_rx_db,
+   output sdi_rx_db,
+
+   output sen_rx_adc,
+   output sclk_rx_adc,
+   input sdo_rx_adc,
+   output sdi_rx_adc,
+
+   output sen_rx_dac,
+   output sclk_rx_dac,
+   output sdi_rx_dac,
+
+   // DB IO Pins
+   inout [15:0] io_tx,
+   inout [15:0] io_rx,
+
+   // SPI Flash
+   output flash_cs,
+   output flash_clk,
+   output flash_mosi,
+   input flash_miso
+   );
+
+   // FPGA-specific pins connections
+   wire 	aux_clk = PHY_CLK;
+
+   wire 	clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+
+   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+   defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+   
+   wire 	exp_pps_in;
+   IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+   defparam 	exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+   
+   wire 	exp_pps_out;
+   OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+   defparam 	exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+   reg [5:0] 	clock_ready_d;
+   always @(posedge aux_clk)
+     clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+
+   wire 	dcm_rst = ~&clock_ready_d & |clock_ready_d;
+   wire 	clk_muxed = clock_ready ? clk_fpga : aux_clk;
+
+   wire 	adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+   assign 	adc_oen_a = ~adc_oe_a;
+   assign 	adc_oen_b = ~adc_oe_b;
+   assign 	adc_pdn_a = ~adc_on_a; 	
+   assign 	adc_pdn_b = ~adc_on_b; 	
+
+   // Handle Clocks
+   DCM DCM_INST (.CLKFB(dsp_clk), 
+                 .CLKIN(clk_muxed), 
+                 .DSSEN(0), 
+                 .PSCLK(0), 
+                 .PSEN(0), 
+                 .PSINCDEC(0), 
+                 .RST(dcm_rst), 
+                 .CLKDV(clk_div), 
+                 .CLKFX(), 
+                 .CLKFX180(), 
+                 .CLK0(dcm_out), 
+                 .CLK2X(), 
+                 .CLK2X180(), 
+                 .CLK90(), 
+                 .CLK180(), 
+                 .CLK270(), 
+                 .LOCKED(LOCKED_OUT), 
+                 .PSDONE(), 
+                 .STATUS());
+   defparam DCM_INST.CLK_FEEDBACK = "1X";
+   defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST.CLKFX_DIVIDE = 1;
+   defparam DCM_INST.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST.CLKIN_PERIOD = 10.000;
+   defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST.FACTORY_JF = 16'h8080;
+   defparam DCM_INST.PHASE_SHIFT = 0;
+   defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+   BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+   BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+   // I2C -- Don't use external transistors for open drain, the FPGA implements this
+   IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+   IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+   // LEDs are active low outputs
+   wire [4:0] leds_int;
+   assign     leds = ~leds_int;  // drive low to turn on leds
+   
+   // SPI
+   wire 	miso, mosi, sclk_int;
+   assign 	{sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+   
+   assign 	miso = (~sen_clk & sdo) | (~sen_dac & sdo) | 
+		(~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+		(~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+   wire 	GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+   wire [7:0] 	GMII_TXD_unreg;
+   wire 	GMII_GTX_CLK_int;
+   
+   always @(posedge GMII_GTX_CLK_int)
+     begin
+	GMII_TX_EN <= GMII_TX_EN_unreg;
+	GMII_TX_ER <= GMII_TX_ER_unreg;
+	GMII_TXD <= GMII_TXD_unreg;
+     end
+
+   OFDDRRSE OFDDRRSE_gmii_inst 
+     (.Q(GMII_GTX_CLK),      // Data output (connect directly to top-level port)
+      .C0(GMII_GTX_CLK_int),    // 0 degree clock input
+      .C1(~GMII_GTX_CLK_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   
+   wire ser_tklsb_unreg, ser_tkmsb_unreg;
+   wire [15:0] ser_t_unreg;
+   wire        ser_tx_clk_int;
+   
+   always @(posedge ser_tx_clk_int)
+     begin
+	ser_tklsb <= ser_tklsb_unreg;
+	ser_tkmsb <= ser_tkmsb_unreg;
+	ser_t <= ser_t_unreg;
+     end
+
+   assign ser_tx_clk = clk_fpga;
+
+   reg [15:0] ser_r_int;
+   reg 	      ser_rklsb_int, ser_rkmsb_int;
+
+   always @(posedge ser_rx_clk)
+     begin
+	ser_r_int <= ser_r;
+	ser_rklsb_int <= ser_rklsb;
+	ser_rkmsb_int <= ser_rkmsb;
+     end
+   
+   /*
+   OFDDRRSE OFDDRRSE_serdes_inst 
+     (.Q(ser_tx_clk),      // Data output (connect directly to top-level port)
+      .C0(ser_tx_clk_int),    // 0 degree clock input
+      .C1(~ser_tx_clk_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   */
+   u2_core u2_core(.dsp_clk           (dsp_clk),
+		     .wb_clk            (wb_clk),
+		     .clock_ready       (clock_ready),
+		     .clk_to_mac	(clk_to_mac),
+		     .pps_in		(pps_in),
+		     .leds		(leds_int),
+		     .debug		(debug[31:0]),
+		     .debug_clk		(debug_clk[1:0]),
+		     .exp_pps_in	(exp_pps_in),
+		     .exp_pps_out	(exp_pps_out),
+		     .GMII_COL		(GMII_COL),
+		     .GMII_CRS		(GMII_CRS),
+		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
+		     .GMII_TX_EN	(GMII_TX_EN_unreg),
+		     .GMII_TX_ER	(GMII_TX_ER_unreg),
+		     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
+		     .GMII_TX_CLK	(GMII_TX_CLK),
+		     .GMII_RXD		(GMII_RXD[7:0]),
+		     .GMII_RX_CLK	(GMII_RX_CLK),
+		     .GMII_RX_DV	(GMII_RX_DV),
+		     .GMII_RX_ER	(GMII_RX_ER),
+		     .MDIO		(MDIO),
+		     .MDC		(MDC),
+		     .PHY_INTn		(PHY_INTn),
+		     .PHY_RESETn	(PHY_RESETn),
+		     .PHY_CLK		(PHY_CLK),
+		     .ser_enable	(ser_enable),
+		     .ser_prbsen	(ser_prbsen),
+		     .ser_loopen	(ser_loopen),
+		     .ser_rx_en		(ser_rx_en),
+		     .ser_tx_clk	(ser_tx_clk_int),
+		     .ser_t		(ser_t_unreg[15:0]),
+		     .ser_tklsb		(ser_tklsb_unreg),
+		     .ser_tkmsb		(ser_tkmsb_unreg),
+		     .ser_rx_clk	(ser_rx_clk),
+		     .ser_r		(ser_r_int[15:0]),
+		     .ser_rklsb		(ser_rklsb_int),
+		     .ser_rkmsb		(ser_rkmsb_int),
+		     .cpld_start        (cpld_start),
+		     .cpld_mode         (cpld_mode),
+		     .cpld_done         (cpld_done),
+		     .cpld_din          (cpld_din),
+		     .cpld_clk          (cpld_clk),
+		     .cpld_detached     (cpld_detached),
+		     .adc_a		(adc_a[13:0]),
+		     .adc_ovf_a		(adc_ovf_a),
+		     .adc_on_a		(adc_on_a),
+		     .adc_oe_a		(adc_oe_a),
+		     .adc_b		(adc_b[13:0]),
+		     .adc_ovf_b		(adc_ovf_b),
+		     .adc_on_b		(adc_on_b),
+		     .adc_oe_b		(adc_oe_b),
+		     .dac_a		(dac_a[15:0]),
+		     .dac_b		(dac_b[15:0]),
+		     .scl_pad_i		(scl_pad_i),
+		     .scl_pad_o		(scl_pad_o),
+		     .scl_pad_oen_o	(scl_pad_oen_o),
+		     .sda_pad_i		(sda_pad_i),
+		     .sda_pad_o		(sda_pad_o),
+		     .sda_pad_oen_o	(sda_pad_oen_o),
+		     .clk_en		(clk_en[1:0]),
+		     .clk_sel		(clk_sel[1:0]),
+		     .clk_func		(clk_func),
+		     .clk_status	(clk_status),
+		     .sclk		(sclk_int),
+		     .mosi		(mosi),
+		     .miso		(miso),
+		     .sen_clk		(sen_clk),
+		     .sen_dac		(sen_dac),
+		     .sen_tx_db		(sen_tx_db),
+		     .sen_tx_adc	(sen_tx_adc),
+		     .sen_tx_dac	(sen_tx_dac),
+		     .sen_rx_db		(sen_rx_db),
+		     .sen_rx_adc	(sen_rx_adc),
+		     .sen_rx_dac	(sen_rx_dac),
+		     .io_tx		(io_tx[15:0]),
+		     .io_rx		(io_rx[15:0]),
+		     .RAM_D             (RAM_D),
+		     .RAM_A             (RAM_A),
+		     .RAM_CE1n          (RAM_CE1n),
+		     .RAM_CENn          (RAM_CENn),
+		     .RAM_CLK           (RAM_CLK),
+		     .RAM_WEn           (RAM_WEn),
+		     .RAM_OEn           (RAM_OEn),
+		     .RAM_LDn           (RAM_LDn), 
+		     .uart_tx_o         (uart_tx_o),
+		     //.uart_rx_i         (uart_rx_i),
+		     .uart_rx_i         (),
+		     .uart_baud_o       (),
+		     .sim_mode          (1'b0),
+		     .clock_divider     (2)
+		     );
+   
+endmodule // u2plus