Added to DCM's and some BUFG's to align the internal 125MHz clock edge with its presentation externally at the NoBL SRAM.

Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA.
This hasn't been verified as working on a USRP2 yet.

4 files changed, 100 insertions, 5 deletions

diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v
index 9ba3cc136..a5963f6b1 100755
--- a/usrp2/top/u2_rev3/u2_core.v
+++ b/usrp2/top/u2_rev3/u2_core.v
@@ -123,7 +123,7 @@ module u2_core
    output [18:0] RAM_A,
    output RAM_CE1n,
    output RAM_CENn,
-   output RAM_CLK,
+ //  output RAM_CLK,
    output RAM_WEn,
    output RAM_OEn,
    output RAM_LDn,
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v
index 189c4966f..b5d0ed72f 100644
--- a/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/usrp2/top/u2_rev3/u2_core_udp.v
@@ -125,7 +125,7 @@ module u2_core
    output [18:0] RAM_A,
    output RAM_CE1n,
    output RAM_CENn,
-   output RAM_CLK,
+ //  output RAM_CLK,
    output RAM_WEn,
    output RAM_OEn,
    output RAM_LDn,
@@ -705,7 +705,6 @@ module u2_core
 
    assign RAM_CLK = clk_to_mac;
    
-   
    // /////////////////////////////////////////////////////////////////////////
    // VITA Timing
 
diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf
index bf9569fe4..175fbec8d 100644
--- a/usrp2/top/u2_rev3/u2_rev3.ucf
+++ b/usrp2/top/u2_rev3/u2_rev3.ucf
@@ -324,6 +324,7 @@ NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
 TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
 
 NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
+NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; 
 
 #NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
 #NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v
index 5e32b368a..cef868df9 100644
--- a/usrp2/top/u2_rev3/u2_rev3.v
+++ b/usrp2/top/u2_rev3/u2_rev3.v
@@ -373,14 +373,109 @@ module u2_rev3
 		      );
 	end // block: gen_RAM_D_IO
    endgenerate
+
+   //
+   // DCM edits start here
+   //
+
+ 
+   wire RAM_CLK_buf;
+   wire clk_to_mac_buf;
+   wire clk125_ext_clk0;
+   wire clk125_ext_clk180;
+   wire clk125_ext_clk0_buf;
+   wire clk125_ext_clk180_buf;
+   wire clk125_int_buf;
+   wire clk125_int;
+   
+   IBUFG clk_to_mac_buf_i1 (.I(clk_to_mac), 
+			    .O(clk_to_mac_buf));
    
+   DCM DCM_INST1 (.CLKFB(RAM_CLK_buf), 
+                  .CLKIN(clk_to_mac_buf), 
+                  .DSSEN(1'b0), 
+                  .PSCLK(1'b0), 
+                  .PSEN(1'b0), 
+                  .PSINCDEC(1'b0), 
+                  .RST(clk125_ext_RST_IN), 
+                  .CLK0(clk125_ext_clk0), 
+                  .CLK180(clk125_ext_clk180) );
+   defparam DCM_INST1.CLK_FEEDBACK = "1X";
+   defparam DCM_INST1.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST1.CLKFX_DIVIDE = 1;
+   defparam DCM_INST1.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST1.CLKIN_PERIOD = 8.000;
+   defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST1.FACTORY_JF = 16'h8080;
+   defparam DCM_INST1.PHASE_SHIFT = 0;
+   defparam DCM_INST1.STARTUP_WAIT = "FALSE";
+   
+   IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), 
+			 .O(RAM_CLK_buf));
+   BUFG  clk125_ext_clk0_buf_i1 (.I(clk125_ext_clk0), 
+				   .O(clk125_ext_clk0_buf));
+   BUFG  clk125_ext_clk180_buf_i1 (.I(clk125_ext_clk180), 
+				   .O(clk125_ext_clk180_buf));
+
+   OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK),
+			.C0(clk125_ext_clk0_buf),
+			.C1(clk125_ext_clk180_buf),
+			.CE(1'b1),
+			.D0(1'b1),
+			.D1(1'b0),
+			.R(1'b0),
+			.S(1'b0));
+
+   SRL16 dcm2_rst_i1 (.D(1'b0),
+		      .CLK(clk_to_mac_buf),
+		      .Q(dcm2_rst),
+		      .A0(1'b1),
+		      .A1(1'b1),
+		      .A2(1'b1),
+		      .A3(1'b1));
+   // synthesis attribute init of dcm2_rst_i2 is "000F";
+      
+   DCM DCM_INST2 (.CLKFB(clk125_int_buf), 
+                  .CLKIN(clk_to_mac_buf), 
+                  .DSSEN(1'b0), 
+                  .PSCLK(1'b0), 
+                  .PSEN(1'b0), 
+                  .PSINCDEC(1'b0), 
+                  .RST(clk125_int_RST_IN),
+                  .CLK0(clk125_int));
+   defparam DCM_INST2.CLK_FEEDBACK = "1X";
+   defparam DCM_INST2.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST2.CLKFX_DIVIDE = 1;
+   defparam DCM_INST2.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST2.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST2.CLKIN_PERIOD = 8.000;
+   defparam DCM_INST2.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST2.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST2.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST2.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST2.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST2.FACTORY_JF = 16'h8080;
+   defparam DCM_INST2.PHASE_SHIFT = 0;
+   defparam DCM_INST2.STARTUP_WAIT = "FALSE";
+  
+   BUFG clk125_int_buf_i1 (.I(clk125_int), 
+                           .O(clk125_int_buf));
+   
+   //
+   // DCM edits end here
+   //
    
    
    u2_core #(.RAM_SIZE(32768))
      u2_core(.dsp_clk           (dsp_clk),
 	     .wb_clk            (wb_clk),
 	     .clock_ready       (clock_ready),
-	     .clk_to_mac	(clk_to_mac),
+	     .clk_to_mac	(clk125_int_buf),
 	     .pps_in		(pps_in),
 	     .leds		(leds_int),
 	     .debug		(debug[31:0]),
@@ -463,7 +558,7 @@ module u2_rev3
 	     .RAM_A             (RAM_A),
 	     .RAM_CE1n          (RAM_CE1n),
 	     .RAM_CENn          (RAM_CENn),
-	     .RAM_CLK           (RAM_CLK),
+	//     .RAM_CLK           (RAM_CLK),
 	     .RAM_WEn           (RAM_WEn),
 	     .RAM_OEn           (RAM_OEn),
 	     .RAM_LDn           (RAM_LDn),