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| author | Matt Ettus <matt@ettus.com> | 2010-12-30 10:56:53 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-12-30 10:56:53 -0800 |
| commit | cc1f46382cd51c11b1d8ae175f3c7f86ea3df8e6 (patch) | |
| tree | 3762217c97518792e03e8af596607287b26bf490 /usrp2/top | |
| parent | 19dafcc4ce1b53651cb7e4d471810cc81aa38528 (diff) | |
| download | uhd-cc1f46382cd51c11b1d8ae175f3c7f86ea3df8e6.tar.gz uhd-cc1f46382cd51c11b1d8ae175f3c7f86ea3df8e6.tar.bz2 uhd-cc1f46382cd51c11b1d8ae175f3c7f86ea3df8e6.zip | |
processor can read back vita_time at last pps
Diffstat (limited to 'usrp2/top')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core.v | 14 |
1 files changed, 4 insertions, 10 deletions
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index 30b47b818..0b56636c8 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -180,7 +180,7 @@ module u2_core wire serdes_link_up; wire epoch; wire [31:0] irq; - wire [63:0] vita_time; + wire [63:0] vita_time, vita_time_pps; wire run_rx, run_tx; reg run_rx_d1; @@ -419,13 +419,6 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 - reg [31:0] cycle_count; - always @(posedge wb_clk) - if(wb_rst) - cycle_count <= 0; - else - cycle_count <= cycle_count + 1; - //compatibility number -> increment when the fpga has been sufficiently altered localparam compat_num = 32'd3; @@ -436,7 +429,8 @@ module u2_core .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq), + .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]) ); // ///////////////////////////////////////////////////////////////////////// @@ -724,7 +718,7 @@ module u2_core time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int), + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), .debug(debug_sync)); |