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authorJosh Blum <josh@joshknows.com>2011-11-23 20:02:37 -0800
committerJosh Blum <josh@joshknows.com>2011-11-23 20:02:37 -0800
commit5f520de104cd5ee5ebc42d4e88dc606720953d49 (patch)
treee8e6f7ef7ce5dcfbdf64c0385b34b1a48c5a84dc /usrp2/top
parent52b552f43bc1925ce27b4f49dff1669cb019ecfc (diff)
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usrp2/nseries: restored clock/serdes readback
Diffstat (limited to 'usrp2/top')
-rw-r--r--usrp2/top/N2x0/u2plus_core.v4
-rw-r--r--usrp2/top/USRP2/u2_core.v4
2 files changed, 4 insertions, 4 deletions
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index ba9569778..3ead0db8e 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -435,7 +435,7 @@ module u2plus_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd8, 16'd1}; //major, minor
+ localparam compat_num = {16'd8, 16'd2}; //major, minor
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
@@ -444,7 +444,7 @@ module u2plus_core
.word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
.word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
.word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
- .word11(vita_time[31:0]),.word12(compat_num),.word13({18'b0, button, 13'b0}),
+ .word11(vita_time[31:0]),.word12(compat_num),.word13({18'b0, button, 1'b0, clk_status, serdes_link_up, 10'b0}),
.word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
);
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index bc651978d..bbd0e9337 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -441,7 +441,7 @@ module u2_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd8, 16'd1}; //major, minor
+ localparam compat_num = {16'd8, 16'd2}; //major, minor
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
@@ -450,7 +450,7 @@ module u2_core
.word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
.word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
.word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
- .word11(vita_time[31:0]),.word12(compat_num),.word13(32'b0),
+ .word11(vita_time[31:0]),.word12(compat_num),.word13({20'b0, clk_status, serdes_link_up, 10'b0}),
.word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
);