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| author | Matt Ettus <matt@ettus.com> | 2011-03-03 12:53:50 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-03 12:53:50 -0800 |
| commit | ebc71c8dfaa0a2b122b764d6b059709d83c905bd (patch) | |
| tree | 26eda02441460d7ff4434e736fb37fad99df8997 /usrp2/top | |
| parent | 173f03d981bacb746a865ca661c265e0e45ec3b1 (diff) | |
| download | uhd-ebc71c8dfaa0a2b122b764d6b059709d83c905bd.tar.gz uhd-ebc71c8dfaa0a2b122b764d6b059709d83c905bd.tar.bz2 uhd-ebc71c8dfaa0a2b122b764d6b059709d83c905bd.zip | |
u2/u2p: switch over to 36 bit wide ethernet wrapper
Diffstat (limited to 'usrp2/top')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core.v | 25 |
1 files changed, 6 insertions, 19 deletions
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index 5652673be..747b2c6cb 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -433,32 +433,24 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Ethernet MAC Slave #6 - wire [18:0] rx_f19_data, tx_f19_data; - wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; - - simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 + wire [35:0] rx_f36_data, tx_f36_data; + wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; + + simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 (.clk125(clk_to_mac), .reset(wb_rst), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), .sys_clk(dsp_clk), - .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), - .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), + .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy), + .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); - wire [35:0] rx_f36_data, tx_f36_data; - wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; - //mac rx to eth input... - fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .f19_datain(rx_f19_data), .f19_src_rdy_i(rx_f19_src_rdy), .f19_dst_rdy_o(rx_f19_dst_rdy), - .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); - fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), @@ -470,11 +462,6 @@ module u2_core .datain(rd2_dat), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); - fifo36_to_fifo19 eth_out_fifo36_to_fifo19 - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), - .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); - // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 settings_bus settings_bus |