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| author | Ian Buckley <ian.buckley@gmail.com> | 2010-02-24 10:54:54 -0800 |
|---|---|---|
| committer | Ian Buckley <ian.buckley@gmail.com> | 2010-02-24 10:54:54 -0800 |
| commit | 06ba14e55b200b9aa0314f63b38c08f30613859f (patch) | |
| tree | f7f1122195a123c012f5cf81fcae94f4d7e0d5d6 /usrp2/top | |
| parent | 4f66d0fbff3da2105018492d21ca64b96115aba3 (diff) | |
| download | uhd-06ba14e55b200b9aa0314f63b38c08f30613859f.tar.gz uhd-06ba14e55b200b9aa0314f63b38c08f30613859f.tar.bz2 uhd-06ba14e55b200b9aa0314f63b38c08f30613859f.zip | |
Cut debug bus connection to etherenet MAC to make closing timing easier
Diffstat (limited to 'usrp2/top')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_rev3.v | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 3c35743a3..3a43e4ffe 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -177,6 +177,9 @@ module u2_rev3 BUFG clk_fpga_BUF (.O(clk_fpga),.I(clk_fpga_unbuf)); defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire cpld_clock_buf; + BUFG cpld_clock_BUF (.O(cpld_clock_buf),.I(cpld_clock)); wire exp_pps_in; IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); @@ -314,7 +317,9 @@ module u2_rev3 reg [15:0] ser_r_int; reg ser_rklsb_int, ser_rkmsb_int; - always @(posedge ser_rx_clk) + wire ser_rx_clk_buf; + BUFG ser_rx_clk_BUF (.O(ser_rx_clk_buf),.I(ser_rx_clk)); + always @(posedge ser_rx_clk_buf) begin ser_r_int <= ser_r; ser_rklsb_int <= ser_rklsb; @@ -371,7 +376,7 @@ module u2_rev3 .ser_t (ser_t_unreg[15:0]), .ser_tklsb (ser_tklsb_unreg), .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), + .ser_rx_clk (ser_rx_clk_buf), .ser_r (ser_r_int[15:0]), .ser_rklsb (ser_rklsb_int), .ser_rkmsb (ser_rkmsb_int), |