First cut at passing data buffers around on GPMC bus

3 files changed, 24 insertions, 10 deletions

diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
index 319645af6..3cae74c8a 100644
--- a/usrp2/top/u1e/tb_u1e.v
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+`timescale 1ps / 1ps
 //////////////////////////////////////////////////////////////////////////////////
 
 module tb_u1e();
@@ -20,10 +20,15 @@ module tb_u1e();
    wire [10:1] EM_A;
    wire [1:0]  EM_NBE;
    
-   reg  clk_fpga = 0;
+   reg  clk_fpga = 0, rst_fpga = 1;
    always #15.625 clk_fpga = ~clk_fpga;
+
+   initial #200
+     @(posedge clk_fpga)
+       rst_fpga <= 0;
    
-   u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), 
+		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
 		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
 		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
 		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
index 667372434..066d02ca4 100644
--- a/usrp2/top/u1e/u1e.v
+++ b/usrp2/top/u1e/u1e.v
@@ -21,7 +21,8 @@ module u1e
    IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
    clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
 
-   u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(debug_pb[2]),
+		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
 		     .debug_pb(debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
 		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
 		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 12c566b6c..7feafeda8 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -1,8 +1,7 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
 
 module u1e_core
-  (input clk_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+  (input clk_fpga, input rst_fpga,
+   output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
    input [2:0] debug_pb, input [7:0] dip_sw, output debug_txd, input debug_rxd,
    
    // GPMC
@@ -14,7 +13,8 @@ module u1e_core
    inout [15:0] io_tx, inout [15:0] io_rx
    );
    
-   wire   wb_clk, wb_rst;
+   wire 	wb_clk = clk_fpga;
+   wire 	wb_rst = rst_fpga;
    
    // /////////////////////////////////////////////////////////////////////////////////////
    // GPMC Slave to Wishbone Master
@@ -31,10 +31,18 @@ module u1e_core
 	      .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), 
 	      .EM_NOE(EM_NOE),
 
+	      .rx_have_data(rx_have_data), .tx_have_space(tx_have_space),
+	      
 	      .wb_clk(wb_clk), .wb_rst(wb_rst),
 	      .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
 	      .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
-	      .wb_ack_i(m0_ack));
+	      .wb_ack_i(m0_ack),
+
+	      .ram_clk(wb_clk),
+	      .read_en(read_en), .read_addr(read_addr), .read_data(read_data), 
+	      .read_ready(read_ready), .read_done(read_done),
+	      .write_en(write_en), .write_addr(write_addr), .write_data(write_data), 
+	      .write_ready(write_ready), .write_done(write_done) );
 
    assign wb_clk = clk_fpga;
 
@@ -130,7 +138,7 @@ module u1e_core
 			16'hBEEF;
    assign s0_ack = s0_stb & s0_cyc;
 
-   assign { rx_overrun, rx_have_data, tx_underrun, tx_have_space } = reg_gpios;
+   assign { rx_overrun, tx_underrun } = reg_gpios;
 
    // /////////////////////////////////////////////////////////////////////////////////////
    // Slave 1, UART