gpmc: tighter timing constraints and easier to route gpmc to fifo

1 files changed, 11 insertions, 15 deletions

diff --git a/usrp2/top/E1x0/timing.ucf b/usrp2/top/E1x0/timing.ucf
index 47c250c2f..16f06dab7 100644
--- a/usrp2/top/E1x0/timing.ucf
+++ b/usrp2/top/E1x0/timing.ucf
@@ -3,25 +3,21 @@ NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
 TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;
 
 NET "EM_CLK" TNM_NET = "EM_CLK";
-TIMESPEC "TS_em_clk" = PERIOD "EM_CLK" 12048 ps HIGH 50 %;
+TIMESPEC "TS_em_clk" = PERIOD "EM_CLK" 18867 ps HIGH 50 %;
 
 #constrain GPMC IO
-NET "EM_D<*>" MAXDELAY = 5.5 ns;
-NET "EM_A<*>" MAXDELAY = 5.5 ns;
-NET "EM_NBE<*>" MAXDELAY = 5.5 ns;
-NET "EM_NCS4" MAXDELAY = 5.5 ns;
-NET "EM_NCS6" MAXDELAY = 5.5 ns;
-NET "EM_NWE" MAXDELAY = 5.5 ns;
-NET "EM_NOE" MAXDELAY = 5.5 ns;
+INST "EM_D<*>" TNM = gpmc_net_out;
+INST "EM_D<*>" TNM = gpmc_net;
+INST "EM_A<*>" TNM = gpmc_net;
+INST "EM_NCS4" TNM = gpmc_net;
+INST "EM_NCS6" TNM = gpmc_net;
+INST "EM_NWE" TNM = gpmc_net;
+INST "EM_NOE" TNM = gpmc_net;
+
+TIMEGRP "gpmc_net" OFFSET = IN 5 ns VALID 10 ns BEFORE "EM_CLK" FALLING;
+TIMEGRP "gpmc_net_out" OFFSET = OUT 14 ns AFTER "EM_CLK" RISING; //2 clock cyc per read
 
 #constrain interrupt lines
 NET "overo_gpio144" MAXDELAY = 5.5 ns; #have space
 NET "overo_gpio146" MAXDELAY = 5.5 ns; #have data
 NET "overo_gpio147" MAXDELAY = 5.5 ns; #have msg/aux spi miso
-
-#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
-#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
-#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
-
-#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
-#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;