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authorMatt Ettus <matt@ettus.com>2010-06-10 15:45:58 -0700
committerMatt Ettus <matt@ettus.com>2010-06-10 15:45:58 -0700
commita4b11332ab4f6a24bf4645c0b2770f9578a36f45 (patch)
tree4672f3f43673de1ec925363887f807c91be60696 /usrp2/top
parentb38a1db20233e6d23ffce831c38d67a500e87b51 (diff)
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debug pins
Diffstat (limited to 'usrp2/top')
-rw-r--r--usrp2/top/u1e/u1e_core.v9
1 files changed, 6 insertions, 3 deletions
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 8db995b17..64173ef2d 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -428,13 +428,16 @@ module u1e_core
//assign debug = { phase[23:8], txsync, txblank, tx };
- assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, rx_i[11:0]},
- {rx1_src_rdy, rx1_dst_rdy, rx_src_rdy, rx_dst_rdy, rx_q[11:0]} };
+ assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]},
+ {tx1_src_rdy, tx1_dst_rdy, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} };
+
+ assign debug_gpio_1 = debug_vtd | debug_vtc;
+/*
assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy},
{tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy},
{rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0},
{2'b0, bus_error, debug_gpmc[4:0] },
{misc_gpio[7:0]} };
-
+ */
endmodule // u1e_core