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| author | Matt Ettus <matt@ettus.com> | 2011-03-03 18:10:37 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-03 18:10:37 -0800 |
| commit | 8e27fc0c3c1e14e23f6f66911eb2e1aaaf061484 (patch) | |
| tree | c03979f27afa6aa54cd6d5d926e75358e14a8710 /usrp2/top | |
| parent | 985d82f1c24983cf6809a052cb190ba55f673f30 (diff) | |
| download | uhd-8e27fc0c3c1e14e23f6f66911eb2e1aaaf061484.tar.gz uhd-8e27fc0c3c1e14e23f6f66911eb2e1aaaf061484.tar.bz2 uhd-8e27fc0c3c1e14e23f6f66911eb2e1aaaf061484.zip | |
remove references to old directory
Diffstat (limited to 'usrp2/top')
| -rw-r--r-- | usrp2/top/safe_u2plus/Makefile | 1 | ||||
| -rw-r--r-- | usrp2/top/u1e_passthru/Makefile | 3 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3/Makefile | 1 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3_2rx_iad/Makefile | 1 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3_iad/Makefile | 1 | ||||
| -rw-r--r-- | usrp2/top/u2plus/Makefile | 1 |
6 files changed, 1 insertions, 7 deletions
diff --git a/usrp2/top/safe_u2plus/Makefile b/usrp2/top/safe_u2plus/Makefile index 62a02ff40..b72241050 100644 --- a/usrp2/top/safe_u2plus/Makefile +++ b/usrp2/top/safe_u2plus/Makefile @@ -117,7 +117,6 @@ coregen/fifo_xlnx_512x36_2clk.v \ coregen/fifo_xlnx_512x36_2clk.xco \ coregen/fifo_xlnx_64x36_2clk.v \ coregen/fifo_xlnx_64x36_2clk.xco \ -extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ opencores/aemb/rtl/verilog/aeMB_bpcu.v \ diff --git a/usrp2/top/u1e_passthru/Makefile b/usrp2/top/u1e_passthru/Makefile index d1950629b..f2d835608 100644 --- a/usrp2/top/u1e_passthru/Makefile +++ b/usrp2/top/u1e_passthru/Makefile @@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs -include ../../extram/Makefile.srcs include ../../gpmc/Makefile.srcs ################################################## @@ -51,7 +50,7 @@ passthru.ucf SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) \ $(GPMC_SRCS) ################################################## diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 05ada2476..e9b43491a 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs -include ../../extram/Makefile.srcs include ../../extramfifo/Makefile.srcs diff --git a/usrp2/top/u2_rev3_2rx_iad/Makefile b/usrp2/top/u2_rev3_2rx_iad/Makefile index 5b7ed5a8e..334089839 100644 --- a/usrp2/top/u2_rev3_2rx_iad/Makefile +++ b/usrp2/top/u2_rev3_2rx_iad/Makefile @@ -120,7 +120,6 @@ eth/rtl/verilog/flow_ctrl_tx.v \ eth/rtl/verilog/miim/eth_clockgen.v \ eth/rtl/verilog/miim/eth_outputcontrol.v \ eth/rtl/verilog/miim/eth_shiftreg.v \ -extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ opencores/aemb/rtl/verilog/aeMB_bpcu.v \ diff --git a/usrp2/top/u2_rev3_iad/Makefile b/usrp2/top/u2_rev3_iad/Makefile index 5ae8846dd..15df9e43e 100644 --- a/usrp2/top/u2_rev3_iad/Makefile +++ b/usrp2/top/u2_rev3_iad/Makefile @@ -120,7 +120,6 @@ eth/rtl/verilog/flow_ctrl_tx.v \ eth/rtl/verilog/miim/eth_clockgen.v \ eth/rtl/verilog/miim/eth_outputcontrol.v \ eth/rtl/verilog/miim/eth_shiftreg.v \ -extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ opencores/aemb/rtl/verilog/aeMB_bpcu.v \ diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile index c38bd3ec1..38400ce62 100644 --- a/usrp2/top/u2plus/Makefile +++ b/usrp2/top/u2plus/Makefile @@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs -include ../../extram/Makefile.srcs include ../../extramfifo/Makefile.srcs |