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| author | Josh Blum <josh@joshknows.com> | 2012-01-28 14:26:53 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-01-28 14:26:53 -0800 |
| commit | 15a717c0ad95bb93b6740a187afbc781a860a39d (patch) | |
| tree | 1c3863a059220c46e911e741161188ab69b8765f /usrp2/top | |
| parent | 9f9729993197839d8be950d69eca4456c8e41323 (diff) | |
| download | uhd-15a717c0ad95bb93b6740a187afbc781a860a39d.tar.gz uhd-15a717c0ad95bb93b6740a187afbc781a860a39d.tar.bz2 uhd-15a717c0ad95bb93b6740a187afbc781a860a39d.zip | |
dsp rework: added double buffer interface to vita tx
Diffstat (limited to 'usrp2/top')
| -rw-r--r-- | usrp2/top/B100/u1plus_core.v | 2 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v | 2 | ||||
| -rw-r--r-- | usrp2/top/N2x0/u2plus_core.v | 3 | ||||
| -rw-r--r-- | usrp2/top/USRP2/u2_core.v | 3 |
4 files changed, 6 insertions, 4 deletions
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index c61d836d0..b9a7e55a2 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -213,7 +213,7 @@ module u1plus_core wire [31:0] sample_tx; wire strobe_tx; - vita_tx_chain #(.BASE(SR_TX_CTRL), + vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), .DSP_NUMBER(0)) diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index 5bf78bad2..d3495707d 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -218,7 +218,7 @@ module u1e_core wire [31:0] sample_tx; wire strobe_tx; - vita_tx_chain #(.BASE(SR_TX_CTRL), + vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), .DSP_NUMBER(0)) diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v index f3405e63a..0ee66d170 100644 --- a/usrp2/top/N2x0/u2plus_core.v +++ b/usrp2/top/N2x0/u2plus_core.v @@ -170,6 +170,7 @@ module u2plus_core // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo localparam DSP_RX_FIFOSIZE = 10; + localparam DSP_TX_FIFOSIZE = 10; localparam ETH_TX_FIFOSIZE = 9; localparam ETH_RX_FIFOSIZE = 11; localparam SERDES_TX_FIFOSIZE = 9; @@ -659,7 +660,7 @@ module u2plus_core wire [31:0] sample_tx; wire strobe_tx; - vita_tx_chain #(.BASE(SR_TX_CTRL), + vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), .DSP_NUMBER(0)) diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index 6c1a418d5..746853fbf 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -175,6 +175,7 @@ module u2_core // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo localparam DSP_RX_FIFOSIZE = 10; + localparam DSP_TX_FIFOSIZE = 10; localparam ETH_TX_FIFOSIZE = 9; localparam ETH_RX_FIFOSIZE = 11; localparam SERDES_TX_FIFOSIZE = 9; @@ -645,7 +646,7 @@ module u2_core wire [31:0] sample_tx; wire strobe_tx; - vita_tx_chain #(.BASE(SR_TX_CTRL), + vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), .DSP_NUMBER(0)) |