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| author | Matt Ettus <matt@ettus.com> | 2011-05-23 18:21:09 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-06-07 14:42:58 -0700 |
| commit | 9451cb630962216492496f2f13d43ab2d08bde5d (patch) | |
| tree | ddc346598a175481bff70fa9d8462c855c3ce872 /usrp2/top/u2plus | |
| parent | 58fe69310016580481d739cd3638633c446b5747 (diff) | |
| download | uhd-9451cb630962216492496f2f13d43ab2d08bde5d.tar.gz uhd-9451cb630962216492496f2f13d43ab2d08bde5d.tar.bz2 uhd-9451cb630962216492496f2f13d43ab2d08bde5d.zip | |
u2p: FPGA internal termination on the clock line from ADC
Diffstat (limited to 'usrp2/top/u2plus')
| -rw-r--r-- | usrp2/top/u2plus/capture_ddrlvds.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/u2plus/capture_ddrlvds.v b/usrp2/top/u2plus/capture_ddrlvds.v index 2bf114988..d263e0cfa 100644 --- a/usrp2/top/u2plus/capture_ddrlvds.v +++ b/usrp2/top/u2plus/capture_ddrlvds.v @@ -14,7 +14,7 @@ module capture_ddrlvds wire [(2*WIDTH)-1:0] out_pre1; reg [(2*WIDTH)-1:0] out_pre2; - IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("FALSE")) + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); genvar i; @@ -29,7 +29,7 @@ module capture_ddrlvds end endgenerate - always @(negedge clk) + always @(posedge clk) out_pre2 <= out_pre1; always @(posedge clk) |