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authorJosh Blum <josh@joshknows.com>2011-03-17 13:28:24 -0700
committerJosh Blum <josh@joshknows.com>2011-03-17 13:28:24 -0700
commitbe2c1b95c1d6f4ad2ea663bb926a04463edb9358 (patch)
tree08efc2c4a98d06d600110efc7c88982a493b16cd /usrp2/top/u2plus
parent37fa8da55ecc1a51c63982c3d75aef725f99bf55 (diff)
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reverted zpu stack pointer change, incremented fpga compat number
Diffstat (limited to 'usrp2/top/u2plus')
-rw-r--r--usrp2/top/u2plus/u2plus_core.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v
index d3d80cc79..22e181caf 100644
--- a/usrp2/top/u2plus/u2plus_core.v
+++ b/usrp2/top/u2plus/u2plus_core.v
@@ -313,7 +313,7 @@ module u2plus_core
.we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr),
.dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc),
// Interrupts and exceptions
- .stack_start(16'h3ff8), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0));
+ .zpu_status(zpu_status), .interrupt(proc_int & 1'b0));
// /////////////////////////////////////////////////////////////////////////
// Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone
@@ -411,7 +411,7 @@ module u2plus_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = 32'd5;
+ localparam compat_num = 32'd6;
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),