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| author | Matt Ettus <matt@ettus.com> | 2010-07-21 16:21:14 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-07-21 16:21:14 -0700 |
| commit | ef662b0c952f8e22ba760917f3781279471d69dc (patch) | |
| tree | f0c9b8c441becd12eaa811013f4cd62b889176a6 /usrp2/top/u2plus | |
| parent | e161ad7c61d88cac0ec85a972a64af8fe4449fce (diff) | |
| download | uhd-ef662b0c952f8e22ba760917f3781279471d69dc.tar.gz uhd-ef662b0c952f8e22ba760917f3781279471d69dc.tar.bz2 uhd-ef662b0c952f8e22ba760917f3781279471d69dc.zip | |
capitalization matching
Diffstat (limited to 'usrp2/top/u2plus')
| -rw-r--r-- | usrp2/top/u2plus/u2plus.v | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index e382b1aa4..d1a9166ac 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -125,6 +125,10 @@ module u2plus input flash_miso ); + wire CLK_TO_MAC_int, CLK_TO_MAC_int2; + IBUFG phyclk (.O(CLK_TO_MAC_int), .I(CLK_TO_MAC)); + BUFG phyclk2 (.O(CLK_TO_MAC_int2), .I(CLK_TO_MAC_int)); + // FPGA-specific pins connections wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; @@ -289,7 +293,7 @@ module u2plus u2plus_core u2p_c(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), + .clk_to_mac (CLK_TO_MAC), .pps_in (pps_in), .leds (leds_int), .debug (debug[31:0]), |