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| author | Josh Blum <josh@joshknows.com> | 2011-01-04 16:50:14 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-01-04 16:50:14 -0800 |
| commit | 71b24ebf00d5549c97e1341594948232e33b1807 (patch) | |
| tree | cbdff2ce481a6cd82d434285ad0bc16f7b3fcae6 /usrp2/top/u2plus | |
| parent | 8fda3238d3c169df96afd170d7eb7d7a8685660b (diff) | |
| parent | a83e88f8233fbea7ec60230acb04a573b9902a8b (diff) | |
| download | uhd-71b24ebf00d5549c97e1341594948232e33b1807.tar.gz uhd-71b24ebf00d5549c97e1341594948232e33b1807.tar.bz2 uhd-71b24ebf00d5549c97e1341594948232e33b1807.zip | |
Merge branch 'cordic_policy' into next
Conflicts:
usrp2/top/u2_rev3/u2_core.v
usrp2/top/u2plus/u2plus_core.v
Diffstat (limited to 'usrp2/top/u2plus')
| -rw-r--r-- | usrp2/top/u2plus/u2plus_core.v | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index c152f083e..4ec00f995 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -173,7 +173,7 @@ module u2plus_core wire serdes_link_up; wire epoch; wire [31:0] irq; - wire [63:0] vita_time; + wire [63:0] vita_time, vita_time_pps; wire run_rx, run_tx; // /////////////////////////////////////////////////////////////////////////////////////////////// @@ -406,13 +406,6 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 - reg [31:0] cycle_count; - always @(posedge wb_clk) - if(wb_rst) - cycle_count <= 0; - else - cycle_count <= cycle_count + 1; - //compatibility number -> increment when the fpga has been sufficiently altered localparam compat_num = 32'd4; @@ -423,7 +416,8 @@ module u2plus_core .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count) + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq), + .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]) ); // ///////////////////////////////////////////////////////////////////////// @@ -722,10 +716,13 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////// // VITA Timing + wire [31:0] debug_sync; + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int), - .exp_time_in(exp_time_in), .exp_time_out(exp_time_out)); + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), + .debug(debug_sync)); // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins |