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| author | Ian Buckley <ian.buckley@gmail.com> | 2010-10-20 15:45:44 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-11 12:10:35 -0800 |
| commit | aa9643f60e91d00cd7990acde44efad17c2509ed (patch) | |
| tree | 20214c4b511485d8d68326d5a55ef2a54f24a556 /usrp2/top/u2plus/u2plus.ucf | |
| parent | 7e75951d263c00e9f84bdf14d6176680cb3de833 (diff) | |
| download | uhd-aa9643f60e91d00cd7990acde44efad17c2509ed.tar.gz uhd-aa9643f60e91d00cd7990acde44efad17c2509ed.tar.bz2 uhd-aa9643f60e91d00cd7990acde44efad17c2509ed.zip | |
Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by default
Derived RAMCLK from 270degree offset of principle core DCM giving
theoretical 2.5nS timing advance on RAM_CLK relative to RAM_* signals.
Diffstat (limited to 'usrp2/top/u2plus/u2plus.ucf')
| -rwxr-xr-x | usrp2/top/u2plus/u2plus.ucf | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf index 3717b3d91..54dfd2a33 100755 --- a/usrp2/top/u2plus/u2plus.ucf +++ b/usrp2/top/u2plus/u2plus.ucf @@ -415,10 +415,10 @@ TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; -NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE; -PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; +#NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; -NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE; -PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; +#NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; |