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| author | Josh Blum <josh@joshknows.com> | 2010-12-17 19:02:14 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-12-17 19:02:14 -0800 |
| commit | 110070fe371e521c0f20cbbb1b1da66312cb4d74 (patch) | |
| tree | 73d68784058b23846dd001c53b2598f066ada31e /usrp2/top/u2_rev3 | |
| parent | a96f39ef767ffcecac4a1cb7d20584fb7bd1e11a (diff) | |
| download | uhd-110070fe371e521c0f20cbbb1b1da66312cb4d74.tar.gz uhd-110070fe371e521c0f20cbbb1b1da66312cb4d74.tar.bz2 uhd-110070fe371e521c0f20cbbb1b1da66312cb4d74.zip | |
usrp-n210: almost working w/ packet router + zpu
added stack start signal to zpu
removed wb perifs in n210 out of 0-16k
added reset controller for main app
rewire cpu addr line after booted use 0-16k
Diffstat (limited to 'usrp2/top/u2_rev3')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core.v | 16 |
1 files changed, 3 insertions, 13 deletions
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index 97de38a82..66c951638 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -306,18 +306,8 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Processor -// aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) -// aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), -// // Instruction Wishbone bus to I-RAM -// .if_adr(if_adr), -// .if_dat(if_dat), -// // Data Wishbone bus to system bus fabric -// .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), -// .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), -// // Interrupts and exceptions -// .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - //assign bus_error = m0_err | m0_rty; + + assign bus_error = m0_err | m0_rty; wire [63:0] zpu_status; zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) @@ -326,7 +316,7 @@ module u2_core .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + .stack_start(16'h3ff8), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); // ///////////////////////////////////////////////////////////////////////// // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone |