diff options
| author | Matt Ettus <matt@ettus.com> | 2010-08-25 17:44:17 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-08-25 17:44:17 -0700 |
| commit | 7c057ae28c7dda5f60944fdf79c2bafa081b9bfe (patch) | |
| tree | 463f59ff50e2d87a9994b8451c3a4013e55d55af /usrp2/top/u2_rev3 | |
| parent | 652b82a6b0bd8694a4cdef00c7146cc367f75e7b (diff) | |
| download | uhd-7c057ae28c7dda5f60944fdf79c2bafa081b9bfe.tar.gz uhd-7c057ae28c7dda5f60944fdf79c2bafa081b9bfe.tar.bz2 uhd-7c057ae28c7dda5f60944fdf79c2bafa081b9bfe.zip | |
Clean up iq swapping on RX. It is now swapped in the top level.
widened muxes to 4 bits to match tx side and handle more ADCs in future
Diffstat (limited to 'usrp2/top/u2_rev3')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core_udp.v | 2 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3/u2_rev3.v | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 124930c23..c9502898b 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -425,7 +425,7 @@ module u2_core cycle_count <= cycle_count + 1; //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd1; + localparam compat_num = 32'd2; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 3a43e4ffe..d5b382c19 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -205,10 +205,10 @@ module u2_rev3 always @(posedge dsp_clk) begin - adc_a_reg1 <= adc_a; - adc_b_reg1 <= adc_b; - adc_ovf_a_reg1 <= adc_ovf_a; - adc_ovf_b_reg1 <= adc_ovf_b; + adc_a_reg1 <= adc_b; // I and Q on RX are swapped in layout + adc_b_reg1 <= adc_a; + adc_ovf_a_reg1 <= adc_ovf_b; + adc_ovf_b_reg1 <= adc_ovf_a; end always @(posedge dsp_clk) |