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| author | Matt Ettus <matt@ettus.com> | 2010-05-16 18:40:53 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-16 18:40:53 -0700 |
| commit | 87ab0dce6f96216d72d4be7b0a5d4a26a7dba598 (patch) | |
| tree | 7f6c006f70f204c91b403b7ed6b79b1932a7aeb2 /usrp2/top/u2_rev3 | |
| parent | fbe639c25af74ee047d724dde0927cc96d343b0e (diff) | |
| download | uhd-87ab0dce6f96216d72d4be7b0a5d4a26a7dba598.tar.gz uhd-87ab0dce6f96216d72d4be7b0a5d4a26a7dba598.tar.bz2 uhd-87ab0dce6f96216d72d4be7b0a5d4a26a7dba598.zip | |
settings bus to dsp_clk now uses clock crossing fifo
Diffstat (limited to 'usrp2/top/u2_rev3')
| -rw-r--r-- | usrp2/top/u2_rev3/Makefile | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 81d787566..80d09acb7 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -70,6 +70,7 @@ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ control_lib/setting_reg.v \ control_lib/settings_bus.v \ +control_lib/settings_bus_crossclock.v \ control_lib/srl.v \ control_lib/system_control.v \ control_lib/wb_1master.v \ @@ -119,6 +120,8 @@ coregen/fifo_xlnx_512x36_2clk.v \ coregen/fifo_xlnx_512x36_2clk.xco \ coregen/fifo_xlnx_64x36_2clk.v \ coregen/fifo_xlnx_64x36_2clk.xco \ +coregen/fifo_xlnx_16x40_2clk.v \ +coregen/fifo_xlnx_16x40_2clk.xco \ extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ |