diff options
| author | Matt Ettus <matt@ettus.com> | 2010-05-12 16:10:08 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-12 16:10:08 -0700 |
| commit | 4eef4015672ffafb56d66feb57848772f42b54e3 (patch) | |
| tree | e89d11e9281462719114896332f548ea66fbfd13 /usrp2/top/u2_rev3 | |
| parent | fd4bdced70e5089434ec736b5938456219bda068 (diff) | |
| download | uhd-4eef4015672ffafb56d66feb57848772f42b54e3.tar.gz uhd-4eef4015672ffafb56d66feb57848772f42b54e3.tar.bz2 uhd-4eef4015672ffafb56d66feb57848772f42b54e3.zip | |
move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing
Diffstat (limited to 'usrp2/top/u2_rev3')
| -rw-r--r-- | usrp2/top/u2_rev3/Makefile | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 867fb5cab..af93700c5 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -70,6 +70,7 @@ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ control_lib/setting_reg.v \ control_lib/settings_bus.v \ +control_lib/settings_bus_crossclock.v \ control_lib/srl.v \ control_lib/system_control.v \ control_lib/wb_1master.v \ @@ -134,6 +135,8 @@ coregen/fifo_xlnx_64x36_2clk.v \ coregen/fifo_xlnx_64x36_2clk.xco \ coregen/fifo_xlnx_16x19_2clk.v \ coregen/fifo_xlnx_16x19_2clk.xco \ +coregen/fifo_xlnx_16x40_2clk.v \ +coregen/fifo_xlnx_16x40_2clk.xco \ extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ |