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authorMatt Ettus <matt@ettus.com>2010-10-06 16:17:13 -0700
committerMatt Ettus <matt@ettus.com>2010-10-06 16:17:13 -0700
commit1715dd3cbbe41fff273e5b8a407595903cbd491a (patch)
tree956caa54f1945950db78e47f3a8678c53d618733 /usrp2/top/u2_rev3
parent1c3dfe21f8bacbf762b440a23ce652a879288615 (diff)
parentc07bc03b4f0fe6210f3bfc6ecdc079487d882f7d (diff)
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Merge branch 'ise12' into efifo_merge_dcm
* ise12: fix timing problem on DAC output bus clean up DAC inversion and swapping to match schematics Clean up iq swapping on RX. It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future
Diffstat (limited to 'usrp2/top/u2_rev3')
-rw-r--r--usrp2/top/u2_rev3/u2_core_udp.v2
-rw-r--r--usrp2/top/u2_rev3/u2_rev3.v15
2 files changed, 10 insertions, 7 deletions
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v
index bcbaa1f30..2cf7fe5ee 100644
--- a/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/usrp2/top/u2_rev3/u2_core_udp.v
@@ -427,7 +427,7 @@ module u2_core
cycle_count <= cycle_count + 1;
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = 32'd1;
+ localparam compat_num = 32'd2;
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v
index 53f1e0a14..4f7f9bf1a 100644
--- a/usrp2/top/u2_rev3/u2_rev3.v
+++ b/usrp2/top/u2_rev3/u2_rev3.v
@@ -203,12 +203,13 @@ module u2_rev3
reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
+ // ADC A and B are swapped in schematic to facilitate clean layout
always @(posedge dsp_clk)
begin
- adc_a_reg1 <= adc_a;
- adc_b_reg1 <= adc_b;
- adc_ovf_a_reg1 <= adc_ovf_a;
- adc_ovf_b_reg1 <= adc_ovf_b;
+ adc_a_reg1 <= adc_b;
+ adc_b_reg1 <= adc_a;
+ adc_ovf_a_reg1 <= adc_ovf_b;
+ adc_ovf_b_reg1 <= adc_ovf_a;
end
always @(posedge dsp_clk)
@@ -327,8 +328,10 @@ module u2_rev3
end
wire [15:0] dac_a_int, dac_b_int;
- always @(negedge dsp_clk) dac_a <= dac_a_int;
- always @(negedge dsp_clk) dac_b <= dac_b_int;
+ // DAC A and B are swapped in schematic to facilitate clean layout
+ // DAC A is also inverted in schematic to facilitate clean layout
+ always @(posedge dsp_clk) dac_a <= ~dac_b_int;
+ always @(posedge dsp_clk) dac_b <= dac_a_int;
/*
OFDDRRSE OFDDRRSE_serdes_inst