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| author | Josh Blum <josh@joshknows.com> | 2010-11-21 12:19:04 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-23 19:06:59 -0800 |
| commit | 15180da94ec11958ad97aaf0e79c29e2081b8b51 (patch) | |
| tree | ba159ae50f177163609791b49007cd376f1a718a /usrp2/top/u2_rev3 | |
| parent | ff3430ad0623766c752ba91e9462c44975fce602 (diff) | |
| download | uhd-15180da94ec11958ad97aaf0e79c29e2081b8b51.tar.gz uhd-15180da94ec11958ad97aaf0e79c29e2081b8b51.tar.bz2 uhd-15180da94ec11958ad97aaf0e79c29e2081b8b51.zip | |
packet_router: fixed sof bug for cpu (== 1), some logic tweaks, added debug
Diffstat (limited to 'usrp2/top/u2_rev3')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core_udp.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index e9c058527..78cf641f7 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -363,6 +363,8 @@ module u2_core wire [31:0] router_control; wire router_control_changed; + wire [31:0] router_debug; + setting_reg #(.my_addr(SR_BUF_POOL)) sreg(.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), .out(router_control),.changed(router_control_changed)); @@ -375,7 +377,7 @@ module u2_core .stream_clk(dsp_clk), .stream_rst(dsp_rst), .control(router_control), .control_changed(router_control_changed), - .status(status), .sys_int_o(buffer_int), + .status(status), .sys_int_o(buffer_int), .debug(router_debug), .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), |