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| author | Matt Ettus <matt@ettus.com> | 2010-11-11 19:21:36 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-11 19:21:36 -0800 |
| commit | ee48c9abebf25d42301d19767e876405a3b533bb (patch) | |
| tree | fb03994b29e8d6a0b64fac9f9f26240be85c819e /usrp2/top/u2_rev3 | |
| parent | 048dd370496dd128f7d12ac5c40426490c5d6233 (diff) | |
| download | uhd-ee48c9abebf25d42301d19767e876405a3b533bb.tar.gz uhd-ee48c9abebf25d42301d19767e876405a3b533bb.tar.bz2 uhd-ee48c9abebf25d42301d19767e876405a3b533bb.zip | |
Add flow control and other small vrt fixes to u2p, minor cleanups
Diffstat (limited to 'usrp2/top/u2_rev3')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core_udp.v | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 3c31d33a9..9e62ee1cc 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -125,7 +125,6 @@ module u2_core output [18:0] RAM_A, output RAM_CE1n, output RAM_CENn, - // output RAM_CLK, output RAM_WEn, output RAM_OEn, output RAM_LDn, @@ -662,7 +661,7 @@ module u2_core wire tx_src_rdy, tx_dst_rdy; wire [31:0] debug_vt; wire clear_tx; - + setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_tx)); @@ -681,11 +680,9 @@ module u2_core .RAM_LDn(RAM_LDn), .RAM_OEn(RAM_OEn), .RAM_CE1n(RAM_CE1n), -// .datain({rd1_flags,rd1_dat}), .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), -// .dataout(tx_data), .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy), |