External FIFO tested in simulation and on USRP2 from decimation 64->8 with current head UHD code.

Apparently operation is "flawless" but more regression and corner case regression could and should be done.
Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good
practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.

4 files changed, 200 insertions, 142 deletions

diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp
index 9962887d4..99effb038 100644
--- a/usrp2/top/u2_rev3/Makefile.udp
+++ b/usrp2/top/u2_rev3/Makefile.udp
@@ -24,6 +24,8 @@ include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../extram/Makefile.srcs
+include ../../extramfifo/Makefile.srcs
+
 
 ##################################################
 # Project Properties
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v
index 3b565ba90..b0c8e6d52 100644
--- a/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/usrp2/top/u2_rev3/u2_core_udp.v
@@ -119,7 +119,9 @@ module u2_core
    inout [15:0] io_rx,
 
    // External RAM
-   inout [17:0] RAM_D,
+   input [17:0] RAM_D_pi,
+   output [17:0] RAM_D_po,   
+   output RAM_D_poe,
    output [18:0] RAM_A,
    output RAM_CE1n,
    output RAM_CENn,
@@ -646,10 +648,28 @@ module u2_core
    wire 	 tx_src_rdy, tx_dst_rdy;
    wire [31:0] 	 debug_vt;
    
-   fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i),
-      .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) );
+   ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.DEPTH(19)) 
+     ext_fifo_i1
+       (
+	.int_clk(dsp_clk),
+	.ext_clk(clk_to_mac),
+	.rst(dsp_rst),
+	.RAM_D_pi(RAM_D_pi),
+	.RAM_D_po(RAM_D_po),
+	.RAM_D_poe(RAM_D_poe),
+	.RAM_A(RAM_A),
+	.RAM_WEn(RAM_WEn),
+	.RAM_CENn(RAM_CENn),
+	.RAM_LDn(RAM_LDn),
+	.RAM_OEn(RAM_OEn),
+	.RAM_CE1n(RAM_CE1n),
+	.datain({rd1_flags,rd1_dat}),
+	.src_rdy_i(rd1_ready_o),               // WRITE
+	.dst_rdy_o(rd1_ready_i),               // not FULL
+	.dataout(tx_data),
+	.src_rdy_o(tx_src_rdy),               // not EMPTY
+	.dst_rdy_i(tx_dst_rdy)
+	);
 
    vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
 		   .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) 
@@ -678,6 +698,9 @@ module u2_core
       .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
       .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
 
+   assign RAM_CLK = clk_to_mac;
+   
+   
    // /////////////////////////////////////////////////////////////////////////
    // VITA Timing
 
diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf
index 6aa699d2a..82d879446 100644
--- a/usrp2/top/u2_rev3/u2_rev3.ucf
+++ b/usrp2/top/u2_rev3/u2_rev3.ucf
@@ -74,49 +74,49 @@ NET "MDC"  LOC = "V18"  ;
 NET "PHY_INTn"  LOC = "AB13"  ; 
 NET "PHY_RESETn"  LOC = "AA19"  ; 
 NET "PHY_CLK"  LOC = "V15"  ; 
-NET "RAM_D[0]"  LOC = "N20"  ;
-NET "RAM_D[1]"  LOC = "N21"  ;
-NET "RAM_D[2]"  LOC = "N22"  ;
-NET "RAM_D[3]"  LOC = "M17"  ;
-NET "RAM_D[4]"  LOC = "M18"  ;
-NET "RAM_D[5]"  LOC = "M19"  ;
-NET "RAM_D[6]"  LOC = "M20"  ;
-NET "RAM_D[7]"  LOC = "M21"  ;
-NET "RAM_D[8]"  LOC = "M22"  ;
-NET "RAM_D[9]"  LOC = "Y22"  ;
-NET "RAM_D[10]"  LOC = "Y21"  ;
-NET "RAM_D[11]"  LOC = "Y20"  ;
-NET "RAM_D[12]"  LOC = "Y19"  ;
-NET "RAM_D[13]"  LOC = "W22"  ;
-NET "RAM_D[14]"  LOC = "W21"  ;
-NET "RAM_D[15]"  LOC = "W20"  ;
-NET "RAM_D[16]"  LOC = "W19"  ;
-NET "RAM_D[17]"  LOC = "V22"  ;
-NET "RAM_A[0]"  LOC = "U21"  ;
-NET "RAM_A[1]"  LOC = "T19"  ;
-NET "RAM_A[2]"  LOC = "V21"  ;
-NET "RAM_A[3]"  LOC = "V20"  ;
-NET "RAM_A[4]"  LOC = "T20"  ;
-NET "RAM_A[5]"  LOC = "T21"  ;
-NET "RAM_A[6]"  LOC = "T22"  ;
-NET "RAM_A[7]"  LOC = "T18"  ;
-NET "RAM_A[8]"  LOC = "R18"  ;
-NET "RAM_A[9]"  LOC = "P19"  ;
-NET "RAM_A[10]"  LOC = "P21"  ;
-NET "RAM_A[11]"  LOC = "P22"  ;
-NET "RAM_A[12]"  LOC = "N19"  ;
-NET "RAM_A[13]"  LOC = "N17"  ;
-NET "RAM_A[14]"  LOC = "N18"  ;
-NET "RAM_A[15]"  LOC = "T17"  ;
-NET "RAM_A[16]"  LOC = "U19"  ;
-NET "RAM_A[17]"  LOC = "U18"  ;
-NET "RAM_A[18]"  LOC = "V19"  ;
-NET "RAM_CE1n"  LOC = "U20"  ; 
-NET "RAM_CENn"  LOC = "P18"  ; 
-NET "RAM_CLK"  LOC = "P17"  ; 
-NET "RAM_WEn"  LOC = "R22"  ; 
-NET "RAM_OEn"  LOC = "R21"  ; 
-NET "RAM_LDn"  LOC = "R19"  ; 
+NET "RAM_D[0]"  LOC = "N20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[1]"  LOC = "N21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[2]"  LOC = "N22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[3]"  LOC = "M17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[4]"  LOC = "M18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[5]"  LOC = "M19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[6]"  LOC = "M20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[7]"  LOC = "M21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[8]"  LOC = "M22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[9]"  LOC = "Y22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[10]"  LOC = "Y21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[11]"  LOC = "Y20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[12]"  LOC = "Y19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[13]"  LOC = "W22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[14]"  LOC = "W21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[15]"  LOC = "W20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[16]"  LOC = "W19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[17]"  LOC = "V22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[0]"  LOC = "U21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[1]"  LOC = "T19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[2]"  LOC = "V21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[3]"  LOC = "V20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[4]"  LOC = "T20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[5]"  LOC = "T21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[6]"  LOC = "T22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[7]"  LOC = "T18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[8]"  LOC = "R18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[9]"  LOC = "P19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[10]"  LOC = "P21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[11]"  LOC = "P22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[12]"  LOC = "N19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[13]"  LOC = "N17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[14]"  LOC = "N18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[15]"  LOC = "T17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[16]"  LOC = "U19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[17]"  LOC = "U18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[18]"  LOC = "V19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_CE1n"  LOC = "U20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_CENn"  LOC = "P18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_CLK"  LOC = "P17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_WEn"  LOC = "R22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_OEn"  LOC = "R21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_LDn"  LOC = "R19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
 NET "ser_enable"  LOC = "W11"  ; 
 NET "ser_prbsen"  LOC = "AA3"  ; 
 NET "ser_loopen"  LOC = "Y4"  ; 
diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v
index bab5a7706..5e32b368a 100644
--- a/usrp2/top/u2_rev3/u2_rev3.v
+++ b/usrp2/top/u2_rev3/u2_rev3.v
@@ -345,100 +345,133 @@ module u2_rev3
       .S(0)       // Synchronous preset input
       );
    */
+
+   wire [17:0] RAM_D_pi;
+   wire [17:0] RAM_D_po;
+   wire        RAM_D_poe;
+   
+   genvar      i;
+
+   //
+   // Instantiate IO for Bidirectional bus to SRAM
+   //
+   
+   generate  
+      for (i=0;i<18;i=i+1)
+        begin : gen_RAM_D_IO
+
+	   IOBUF #(
+		   .DRIVE(12),
+		   .IOSTANDARD("LVCMOS25"),
+		   .SLEW("FAST")
+		   )
+	     RAM_D_i (
+		      .O(RAM_D_pi[i]),
+		      .I(RAM_D_po[i]),
+		      .IO(RAM_D[i]),
+		      .T(RAM_D_poe)
+		      );
+	end // block: gen_RAM_D_IO
+   endgenerate
+   
+   
+   
    u2_core #(.RAM_SIZE(32768))
-	u2_core(.dsp_clk           (dsp_clk),
-		     .wb_clk            (wb_clk),
-		     .clock_ready       (clock_ready),
-		     .clk_to_mac	(clk_to_mac),
-		     .pps_in		(pps_in),
-		     .leds		(leds_int),
-		     .debug		(debug[31:0]),
-		     .debug_clk		(debug_clk[1:0]),
-		     .exp_pps_in	(exp_pps_in),
-		     .exp_pps_out	(exp_pps_out),
-		     .GMII_COL		(GMII_COL),
-		     .GMII_CRS		(GMII_CRS),
-		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
-		     .GMII_TX_EN	(GMII_TX_EN_unreg),
-		     .GMII_TX_ER	(GMII_TX_ER_unreg),
-		     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
-		     .GMII_TX_CLK	(GMII_TX_CLK),
-		     .GMII_RXD		(GMII_RXD[7:0]),
-		     .GMII_RX_CLK	(GMII_RX_CLK),
-		     .GMII_RX_DV	(GMII_RX_DV),
-		     .GMII_RX_ER	(GMII_RX_ER),
-		     .MDIO		(MDIO),
-		     .MDC		(MDC),
-		     .PHY_INTn		(PHY_INTn),
-		     .PHY_RESETn	(PHY_RESETn),
-		     .ser_enable	(ser_enable),
-		     .ser_prbsen	(ser_prbsen),
-		     .ser_loopen	(ser_loopen),
-		     .ser_rx_en		(ser_rx_en),
-		     .ser_tx_clk	(ser_tx_clk_int),
-		     .ser_t		(ser_t_unreg[15:0]),
-		     .ser_tklsb		(ser_tklsb_unreg),
-		     .ser_tkmsb		(ser_tkmsb_unreg),
-		     .ser_rx_clk	(ser_rx_clk_buf),
-		     .ser_r		(ser_r_int[15:0]),
-		     .ser_rklsb		(ser_rklsb_int),
-		     .ser_rkmsb		(ser_rkmsb_int),
-		     .cpld_start        (cpld_start),
-		     .cpld_mode         (cpld_mode),
-		     .cpld_done         (cpld_done),
-		     .cpld_din          (cpld_din),
-		     .cpld_clk          (cpld_clk),
-		     .cpld_detached     (cpld_detached),
-		     .cpld_misc         (cpld_misc),
-		     .cpld_init_b       (cpld_init_b),
-		     .por               (~POR),
-		     .config_success    (config_success),
-		     .adc_a		(adc_a_reg2),
-		     .adc_ovf_a		(adc_ovf_a_reg2),
-		     .adc_on_a		(adc_on_a),
-		     .adc_oe_a		(adc_oe_a),
-		     .adc_b		(adc_b_reg2),
-		     .adc_ovf_b		(adc_ovf_b_reg2),
-		     .adc_on_b		(adc_on_b),
-		     .adc_oe_b		(adc_oe_b),
-		     .dac_a		(dac_a_int),
-		     .dac_b		(dac_b_int),
-		     .scl_pad_i		(scl_pad_i),
-		     .scl_pad_o		(scl_pad_o),
-		     .scl_pad_oen_o	(scl_pad_oen_o),
-		     .sda_pad_i		(sda_pad_i),
-		     .sda_pad_o		(sda_pad_o),
-		     .sda_pad_oen_o	(sda_pad_oen_o),
-		     .clk_en		(clk_en[1:0]),
-		     .clk_sel		(clk_sel[1:0]),
-		     .clk_func		(clk_func),
-		     .clk_status	(clk_status),
-		     .sclk		(sclk_int),
-		     .mosi		(mosi),
-		     .miso		(miso),
-		     .sen_clk		(sen_clk),
-		     .sen_dac		(sen_dac),
-		     .sen_tx_db		(sen_tx_db),
-		     .sen_tx_adc	(sen_tx_adc),
-		     .sen_tx_dac	(sen_tx_dac),
-		     .sen_rx_db		(sen_rx_db),
-		     .sen_rx_adc	(sen_rx_adc),
-		     .sen_rx_dac	(sen_rx_dac),
-		     .io_tx		(io_tx[15:0]),
-		     .io_rx		(io_rx[15:0]),
-		     .RAM_D             (RAM_D),
-		     .RAM_A             (RAM_A),
-		     .RAM_CE1n          (RAM_CE1n),
-		     .RAM_CENn          (RAM_CENn),
-		     .RAM_CLK           (RAM_CLK),
-		     .RAM_WEn           (RAM_WEn),
-		     .RAM_OEn           (RAM_OEn),
-		     .RAM_LDn           (RAM_LDn), 
-		     .uart_tx_o         (uart_tx_o),
-		     .uart_rx_i         (uart_rx_i),
-		     .uart_baud_o       (),
-		     .sim_mode          (1'b0),
-		     .clock_divider     (2)
-		     );
+     u2_core(.dsp_clk           (dsp_clk),
+	     .wb_clk            (wb_clk),
+	     .clock_ready       (clock_ready),
+	     .clk_to_mac	(clk_to_mac),
+	     .pps_in		(pps_in),
+	     .leds		(leds_int),
+	     .debug		(debug[31:0]),
+	     .debug_clk		(debug_clk[1:0]),
+	     .exp_pps_in	(exp_pps_in),
+	     .exp_pps_out	(exp_pps_out),
+	     .GMII_COL		(GMII_COL),
+	     .GMII_CRS		(GMII_CRS),
+	     .GMII_TXD		(GMII_TXD_unreg[7:0]),
+	     .GMII_TX_EN	(GMII_TX_EN_unreg),
+	     .GMII_TX_ER	(GMII_TX_ER_unreg),
+	     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
+	     .GMII_TX_CLK	(GMII_TX_CLK),
+	     .GMII_RXD		(GMII_RXD[7:0]),
+	     .GMII_RX_CLK	(GMII_RX_CLK),
+	     .GMII_RX_DV	(GMII_RX_DV),
+	     .GMII_RX_ER	(GMII_RX_ER),
+	     .MDIO		(MDIO),
+	     .MDC		(MDC),
+	     .PHY_INTn		(PHY_INTn),
+	     .PHY_RESETn	(PHY_RESETn),
+	     .ser_enable	(ser_enable),
+	     .ser_prbsen	(ser_prbsen),
+	     .ser_loopen	(ser_loopen),
+	     .ser_rx_en		(ser_rx_en),
+	     .ser_tx_clk	(ser_tx_clk_int),
+	     .ser_t		(ser_t_unreg[15:0]),
+	     .ser_tklsb		(ser_tklsb_unreg),
+	     .ser_tkmsb		(ser_tkmsb_unreg),
+	     .ser_rx_clk	(ser_rx_clk_buf),
+	     .ser_r		(ser_r_int[15:0]),
+	     .ser_rklsb		(ser_rklsb_int),
+	     .ser_rkmsb		(ser_rkmsb_int),
+	     .cpld_start        (cpld_start),
+	     .cpld_mode         (cpld_mode),
+	     .cpld_done         (cpld_done),
+	     .cpld_din          (cpld_din),
+	     .cpld_clk          (cpld_clk),
+	     .cpld_detached     (cpld_detached),
+	     .cpld_misc         (cpld_misc),
+	     .cpld_init_b       (cpld_init_b),
+	     .por               (~POR),
+	     .config_success    (config_success),
+	     .adc_a		(adc_a_reg2),
+	     .adc_ovf_a		(adc_ovf_a_reg2),
+	     .adc_on_a		(adc_on_a),
+	     .adc_oe_a		(adc_oe_a),
+	     .adc_b		(adc_b_reg2),
+	     .adc_ovf_b		(adc_ovf_b_reg2),
+	     .adc_on_b		(adc_on_b),
+	     .adc_oe_b		(adc_oe_b),
+	     .dac_a		(dac_a_int),
+	     .dac_b		(dac_b_int),
+	     .scl_pad_i		(scl_pad_i),
+	     .scl_pad_o		(scl_pad_o),
+	     .scl_pad_oen_o	(scl_pad_oen_o),
+	     .sda_pad_i		(sda_pad_i),
+	     .sda_pad_o		(sda_pad_o),
+	     .sda_pad_oen_o	(sda_pad_oen_o),
+	     .clk_en		(clk_en[1:0]),
+	     .clk_sel		(clk_sel[1:0]),
+	     .clk_func		(clk_func),
+	     .clk_status	(clk_status),
+	     .sclk		(sclk_int),
+	     .mosi		(mosi),
+	     .miso		(miso),
+	     .sen_clk		(sen_clk),
+	     .sen_dac		(sen_dac),
+	     .sen_tx_db		(sen_tx_db),
+	     .sen_tx_adc	(sen_tx_adc),
+	     .sen_tx_dac	(sen_tx_dac),
+	     .sen_rx_db		(sen_rx_db),
+	     .sen_rx_adc	(sen_rx_adc),
+	     .sen_rx_dac	(sen_rx_dac),
+	     .io_tx		(io_tx[15:0]),
+	     .io_rx		(io_rx[15:0]),
+	     .RAM_D_pi             (RAM_D_pi),
+	     .RAM_D_po             (RAM_D_po),
+	     .RAM_D_poe             (RAM_D_poe),
+	     .RAM_A             (RAM_A),
+	     .RAM_CE1n          (RAM_CE1n),
+	     .RAM_CENn          (RAM_CENn),
+	     .RAM_CLK           (RAM_CLK),
+	     .RAM_WEn           (RAM_WEn),
+	     .RAM_OEn           (RAM_OEn),
+	     .RAM_LDn           (RAM_LDn), 
+	     .uart_tx_o         (uart_tx_o),
+	     .uart_rx_i         (uart_rx_i),
+	     .uart_baud_o       (),
+	     .sim_mode          (1'b0),
+	     .clock_divider     (2)
+	     );
    
 endmodule // u2_rev2