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| author | Josh Blum <josh@joshknows.com> | 2010-12-12 17:54:04 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-12-12 17:54:04 -0800 |
| commit | ab9edbfbcb065b3ec380992b3b5836833ce92b4b (patch) | |
| tree | dc8be06a67a75e8d9b713c62841104e1f619964b /usrp2/top/u2_rev3/u2_rev3.v | |
| parent | b6b5b7b65dca848322941c2df73d1b9f5b6ac907 (diff) | |
| parent | 6c1d4ebdbd2229654976dd672a5433c300dc0d17 (diff) | |
| download | uhd-ab9edbfbcb065b3ec380992b3b5836833ce92b4b.tar.gz uhd-ab9edbfbcb065b3ec380992b3b5836833ce92b4b.tar.bz2 uhd-ab9edbfbcb065b3ec380992b3b5836833ce92b4b.zip | |
Merge branch 'packet_router' into zpu
Conflicts:
usrp2/top/u2_rev3/u2_core.v
Diffstat (limited to 'usrp2/top/u2_rev3/u2_rev3.v')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_rev3.v | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 4f7f9bf1a..f2bba6c50 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -11,10 +11,10 @@ module u2_rev3 input uart_rx_i, // Expansion - input exp_pps_in_p, // Diff - input exp_pps_in_n, // Diff - output exp_pps_out_p, // Diff - output exp_pps_out_n, // Diff + input exp_time_in_p, // Diff + input exp_time_in_n, // Diff + output exp_time_out_p, // Diff + output exp_time_out_n, // Diff // GMII // GMII-CTRL @@ -181,13 +181,13 @@ module u2_rev3 wire cpld_clock_buf; BUFG cpld_clock_BUF (.O(cpld_clock_buf),.I(cpld_clock)); - wire exp_pps_in; - IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); - defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; - wire exp_pps_out; - OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); - defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; reg [5:0] clock_ready_d; always @(posedge clk_fpga) @@ -480,8 +480,8 @@ module u2_rev3 .leds (leds_int), .debug (debug[31:0]), .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), + .exp_time_in (exp_time_in), + .exp_time_out (exp_time_out), .GMII_COL (GMII_COL), .GMII_CRS (GMII_CRS), .GMII_TXD (GMII_TXD_unreg[7:0]), |