Merge branch 'ise12' into efifo_merge_dcm

* ise12:
  fix timing problem on DAC output bus
  clean up DAC inversion and swapping to match schematics
  Clean up iq swapping on RX.  It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future

1 files changed, 9 insertions, 6 deletions

diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v
index 53f1e0a14..4f7f9bf1a 100644
--- a/usrp2/top/u2_rev3/u2_rev3.v
+++ b/usrp2/top/u2_rev3/u2_rev3.v
@@ -203,12 +203,13 @@ module u2_rev3
    reg [13:0] 	 adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
    reg 		 adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
 
+    // ADC A and B are swapped in schematic to facilitate clean layout
    always @(posedge dsp_clk)
      begin
-	adc_a_reg1 <= adc_a;
-	adc_b_reg1 <= adc_b;
-	adc_ovf_a_reg1 <= adc_ovf_a;
-	adc_ovf_b_reg1 <= adc_ovf_b;
+	adc_a_reg1 <= adc_b;
+	adc_b_reg1 <= adc_a;
+	adc_ovf_a_reg1 <= adc_ovf_b;
+	adc_ovf_b_reg1 <= adc_ovf_a;
      end
    
    always @(posedge dsp_clk)
@@ -327,8 +328,10 @@ module u2_rev3
      end
 
    wire [15:0] dac_a_int, dac_b_int;
-   always @(negedge dsp_clk) dac_a <= dac_a_int;
-   always @(negedge dsp_clk) dac_b <= dac_b_int;
+   // DAC A and B are swapped in schematic to facilitate clean layout
+   // DAC A is also inverted in schematic to facilitate clean layout
+   always @(posedge dsp_clk) dac_a <= ~dac_b_int;
+   always @(posedge dsp_clk) dac_b <= dac_a_int;
 
    /*
    OFDDRRSE OFDDRRSE_serdes_inst