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| author | Ian Buckley <ianb@server2.(none)> | 2010-09-01 03:08:11 -0700 |
|---|---|---|
| committer | Ian Buckley <ianb@server2.(none)> | 2010-09-01 03:08:11 -0700 |
| commit | c5295159e9f6eeb9ea72edab18ff97eb55d84692 (patch) | |
| tree | d2f3d9fe01f3774e474a40c62a3e0095e9081bd2 /usrp2/top/u2_rev3/u2_core.v | |
| parent | 09c0420f9068187e5e4146254c7ea769b9c69186 (diff) | |
| download | uhd-c5295159e9f6eeb9ea72edab18ff97eb55d84692.tar.gz uhd-c5295159e9f6eeb9ea72edab18ff97eb55d84692.tar.bz2 uhd-c5295159e9f6eeb9ea72edab18ff97eb55d84692.zip | |
Added to DCM's and some BUFG's to align the internal 125MHz clock edge with its presentation externally at the NoBL SRAM.
Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA.
This hasn't been verified as working on a USRP2 yet.
Diffstat (limited to 'usrp2/top/u2_rev3/u2_core.v')
| -rwxr-xr-x | usrp2/top/u2_rev3/u2_core.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index 9ba3cc136..a5963f6b1 100755 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -123,7 +123,7 @@ module u2_core output [18:0] RAM_A, output RAM_CE1n, output RAM_CENn, - output RAM_CLK, + // output RAM_CLK, output RAM_WEn, output RAM_OEn, output RAM_LDn, |