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| author | Matt Ettus <matt@ettus.com> | 2010-07-01 00:45:20 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:19 -0700 |
| commit | 2d67e1453a47a54cf2c9ae651fc7c03d0292ab68 (patch) | |
| tree | 8b28dd8fb74f5a8e87f2b888590e0e58bf06d107 /usrp2/top/u1plus | |
| parent | 014ea68739c616836bcdfce292c8ab89da26afad (diff) | |
| download | uhd-2d67e1453a47a54cf2c9ae651fc7c03d0292ab68.tar.gz uhd-2d67e1453a47a54cf2c9ae651fc7c03d0292ab68.tar.bz2 uhd-2d67e1453a47a54cf2c9ae651fc7c03d0292ab68.zip | |
progress on gpif interface
Diffstat (limited to 'usrp2/top/u1plus')
| -rw-r--r-- | usrp2/top/u1plus/u1plus_core.v | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index c2718de20..3cdc74835 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -44,7 +44,7 @@ module u1plus_core wire set_stb; // ///////////////////////////////////////////////////////////////////////////////////// - // GPMC Slave to Wishbone Master + // GPIF Slave to Wishbone Master localparam dw = 16; localparam aw = 11; localparam sw = 2; @@ -58,8 +58,6 @@ module u1plus_core wire [35:0] tx_data, rx_data; wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; - reg [15:0] tx_frame_len; - wire [15:0] rx_frame_len; wire [7:0] rate; wire bus_error; @@ -77,7 +75,6 @@ module u1plus_core .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), .debug(debug_gpmc)); wire rx_sof = rx_data[32]; @@ -295,7 +292,6 @@ module u1plus_core reg_leds <= 0; reg_cgen_ctrl <= 2'b11; reg_test <= 0; - tx_frame_len <= 0; xfer_rate <= 0; end else @@ -307,8 +303,6 @@ module u1plus_core reg_cgen_ctrl <= s0_dat_mosi; REG_TEST : reg_test <= s0_dat_mosi; - REG_TX_FRAMELEN : - tx_frame_len <= s0_dat_mosi; REG_XFER_RATE : xfer_rate <= s0_dat_mosi; endcase // case (s0_adr[6:0]) @@ -319,14 +313,12 @@ module u1plus_core assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; - //assign { rx_overrun, tx_underrun } = 0; // reg_test; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : //(s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : - (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; |