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| author | Matt Ettus <matt@ettus.com> | 2011-03-16 16:48:16 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:21 -0700 |
| commit | f04a393d48266f5d3e4f35aaddf12ab3214ae8b4 (patch) | |
| tree | 930b0e5ce8e88d2b269772e13bd06b0a926d8c71 /usrp2/top/u1plus | |
| parent | 39f96a4751e1917a31e940d358399f14d08288fd (diff) | |
| download | uhd-f04a393d48266f5d3e4f35aaddf12ab3214ae8b4.tar.gz uhd-f04a393d48266f5d3e4f35aaddf12ab3214ae8b4.tar.bz2 uhd-f04a393d48266f5d3e4f35aaddf12ab3214ae8b4.zip | |
u1p: use icarus verilog to find warnings
Diffstat (limited to 'usrp2/top/u1plus')
| -rwxr-xr-x | usrp2/top/u1plus/core_compile | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/usrp2/top/u1plus/core_compile b/usrp2/top/u1plus/core_compile new file mode 100755 index 000000000..0d95f704d --- /dev/null +++ b/usrp2/top/u1plus/core_compile @@ -0,0 +1,2 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ u1plus_core.v 2>&1 + |