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authorNick Foster <nick@nerdnetworks.org>2011-04-25 16:26:02 -0700
committerMatt Ettus <matt@ettus.com>2011-05-26 17:31:22 -0700
commit56b133ea0d40de3a9bfcd5ed27fca083a809b084 (patch)
tree06e6485c61beca26c421631ada1519d272213fc4 /usrp2/top/u1plus/u1plus.v
parent42561353c372696337983e74a5c7b690afa2aedd (diff)
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B100: added some packet splitter debug pins, removed debug from GPIO port, swapped I&Q in interleaver
Diffstat (limited to 'usrp2/top/u1plus/u1plus.v')
-rw-r--r--usrp2/top/u1plus/u1plus.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v
index 7e1bd2ea7..9aafef3ce 100644
--- a/usrp2/top/u1plus/u1plus.v
+++ b/usrp2/top/u1plus/u1plus.v
@@ -126,13 +126,13 @@ module u1plus
always @(posedge clk_fpga)
if(rxsync_0)
begin
- rx_i <= rx_a;
- rx_q <= rx_b;
+ rx_i <= rx_b;
+ rx_q <= rx_a;
end
else
begin
- rx_i <= rx_b;
- rx_q <= rx_a;
+ rx_i <= rx_a;
+ rx_q <= rx_b;
end
// /////////////////////////////////////////////////////////////////////////