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| author | Matt Ettus <matt@ettus.com> | 2010-06-14 16:14:30 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:19 -0700 |
| commit | 014ea68739c616836bcdfce292c8ab89da26afad (patch) | |
| tree | 18de12cf4488dd17718b9d59790f248be3342c3d /usrp2/top/u1plus/u1plus.v | |
| parent | e25f67d54ad40479415a5208b8f9a4739a79df30 (diff) | |
| download | uhd-014ea68739c616836bcdfce292c8ab89da26afad.tar.gz uhd-014ea68739c616836bcdfce292c8ab89da26afad.tar.bz2 uhd-014ea68739c616836bcdfce292c8ab89da26afad.zip | |
gpif skeletons
Diffstat (limited to 'usrp2/top/u1plus/u1plus.v')
| -rw-r--r-- | usrp2/top/u1plus/u1plus.v | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v index 6ed478420..370d3e4ea 100644 --- a/usrp2/top/u1plus/u1plus.v +++ b/usrp2/top/u1plus/u1plus.v @@ -24,9 +24,12 @@ module u1plus output [13:0] dac, output TXSYNC, output TXBLANK, input [11:0] adc, input RXSYNC, - input PPS_IN + input PPS_IN, + input reset_n, output reset_codec ); + assign reset_codec = 1; // Believed to be active low + // ///////////////////////////////////////////////////////////////////////// // Clocking wire clk_fpga, clk_fpga_in, reset; |