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| author | Matt Ettus <matt@ettus.com> | 2011-04-16 17:53:09 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:22 -0700 |
| commit | 552e81bf1790c531cbbe4087d6ac93f3baab48d4 (patch) | |
| tree | 3f55da5da422ada70fbf9433bc860a824365a17f /usrp2/top/u1plus/u1plus.v | |
| parent | e9a34b8bd51d639e08f31930266e3425de4f53b3 (diff) | |
| download | uhd-552e81bf1790c531cbbe4087d6ac93f3baab48d4.tar.gz uhd-552e81bf1790c531cbbe4087d6ac93f3baab48d4.tar.bz2 uhd-552e81bf1790c531cbbe4087d6ac93f3baab48d4.zip | |
u1p: implement a signal to indicate a partially full usb lut, to flush it
Diffstat (limited to 'usrp2/top/u1plus/u1plus.v')
| -rw-r--r-- | usrp2/top/u1plus/u1plus.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v index 9d52353db..7e1bd2ea7 100644 --- a/usrp2/top/u1plus/u1plus.v +++ b/usrp2/top/u1plus/u1plus.v @@ -8,7 +8,7 @@ module u1plus // GPIF inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY, - input FX2_PA7_FLAGD, input FX2_PA6_PKTEND, input FX2_PA2_SLOE, + output FX2_PA7_FLAGD, output FX2_PA6_PKTEND, output FX2_PA2_SLOE, input IFCLK, inout SDA_FPGA, inout SCL_FPGA, // I2C @@ -141,7 +141,7 @@ module u1plus .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY), - .gpif_misc({FX2_PA7_FLAGD,FX_PA6_PKTEND,FX2_PA2_SLOE}), + .gpif_misc({FX2_PA7_FLAGD,FX2_PA6_PKTEND,FX2_PA2_SLOE}), .gpif_clk(IFCLK), .db_sda(SDA_FPGA), .db_scl(SCL_FPGA), |