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author | Matt Ettus <matt@ettus.com> | 2010-05-07 10:27:33 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2010-05-07 10:27:33 -0700 |
commit | 45d92a0610582672cea4f1d97d116af00eac7bef (patch) | |
tree | 071b4affe003f55a8d06e0b92e53aa693cbf1696 /usrp2/top/u1e_passthru/passthru.v | |
parent | 2ddaba2d8bdcdda07b949f007d2555cf57c7c8d7 (diff) | |
download | uhd-45d92a0610582672cea4f1d97d116af00eac7bef.tar.gz uhd-45d92a0610582672cea4f1d97d116af00eac7bef.tar.bz2 uhd-45d92a0610582672cea4f1d97d116af00eac7bef.zip |
SPI passthru for programming clock gen chip on brand new boards
Diffstat (limited to 'usrp2/top/u1e_passthru/passthru.v')
-rw-r--r-- | usrp2/top/u1e_passthru/passthru.v | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/usrp2/top/u1e_passthru/passthru.v b/usrp2/top/u1e_passthru/passthru.v new file mode 100644 index 000000000..459c226ee --- /dev/null +++ b/usrp2/top/u1e_passthru/passthru.v @@ -0,0 +1,18 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module passthru + (input overo_gpio0, + output cgen_sclk, + output cgen_sen_b, + output cgen_mosi, + input fpga_cfg_din, + input fpga_cfg_cclk + ); + + assign cgen_sclk = fpga_cfg_cclk; + assign cgen_sen_b = overo_gpio0; + assign cgen_mosi = fpga_cfg_din; + + +endmodule // passthru |