connected spi pins, but the spi core still needs to be redone for 16 bit interfaces

Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs

3 files changed, 60 insertions, 40 deletions

diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf
index f237eb60c..27f507c6b 100644
--- a/usrp2/top/u1e/u1e.ucf
+++ b/usrp2/top/u1e/u1e.ucf
@@ -68,27 +68,43 @@ NET "overo_gpio147"  LOC = "B6"  ;  # rx_overrun
 #NET "overo_txd1"  LOC = "C6"  ;
 #NET "overo_rxd1"  LOC = "D6"  ;
 
+## FTDI UART to USB converter
 NET "FPGA_TXD"  LOC = "U1"  ;
 NET "FPGA_RXD"  LOC = "T6"  ;
 
 #NET "SYSEN"  LOC = "C11"  ;
 
+## I2C
 NET "db_scl"  LOC = "U4"  ;
 NET "db_sda"  LOC = "U5"  ;
-#NET "db_sclk_rx"  LOC = "W3"  ;
-#NET "db_miso_rx"  LOC = "W2"  ;
-#NET "db_mosi_rx"  LOC = "V4"  ;
-#NET "db_sen_rx"  LOC = "V3"  ;
-#NET "db_sclk_tx"  LOC = "Y1"  ;
-#NET "db_miso_tx"  LOC = "W1"  ;
-#NET "db_mosi_tx"  LOC = "R3"  ;
-#NET "db_sen_tx"  LOC = "T4"  ;
 
-## Clock Gen
-#NET "cgen_miso"  LOC = "U2"  ;
-#NET "cgen_mosi"  LOC = "V1"  ;
-#NET "cgen_sclk"  LOC = "R5"  ;
-#NET "cgen_sen_b"  LOC = "T1"  ;
+## SPI
+### DBoard SPI
+NET "db_sclk_rx"  LOC = "W3"  ;
+NET "db_miso_rx"  LOC = "W2"  ;
+NET "db_mosi_rx"  LOC = "V4"  ;
+NET "db_sen_rx"  LOC = "V3"  ;
+NET "db_sclk_tx"  LOC = "Y1"  ;
+NET "db_miso_tx"  LOC = "W1"  ;
+NET "db_mosi_tx"  LOC = "R3"  ;
+NET "db_sen_tx"  LOC = "T4"  ;
+
+### AD9862 SPI and aux SPI Interfaces
+#NET "aux_sdi_codec"  LOC = "F19"  ;
+#NET "aux_sdo_codec"  LOC = "F18"  ;
+#NET "aux_sclk_codec"  LOC = "D21"  ;
+NET "sen_codec"  LOC = "D20"  ;
+NET "mosi_codec"  LOC = "E19"  ;
+NET "miso_codec"  LOC = "F21"  ;
+NET "sclk_codec"  LOC = "E20"  ;
+
+### Clock Gen SPI
+NET "cgen_miso"  LOC = "U2"  ;
+NET "cgen_mosi"  LOC = "V1"  ;
+NET "cgen_sclk"  LOC = "R5"  ;
+NET "cgen_sen_b"  LOC = "T1"  ;
+
+## Clock gen control
 #NET "cgen_st_status"  LOC = "D4"  ;
 #NET "cgen_st_ld"  LOC = "D1"  ;
 #NET "cgen_st_refmon"  LOC = "E1"  ;
@@ -147,17 +163,8 @@ NET "dip_sw<2>"  LOC = "J4"  ;
 NET "dip_sw<1>"  LOC = "J6"  ;
 NET "dip_sw<0>"  LOC = "J7"  ;
 
-## AD9862 Interface
-#NET "aux_sdi_codec"  LOC = "F19"  ;
-#NET "aux_sdo_codec"  LOC = "F18"  ;
-#NET "aux_sclk_codec"  LOC = "D21"  ;
-#NET "reset_codec"  LOC = "D22"  ;
-#NET "sen_codec"  LOC = "D20"  ;
-#NET "mosi_codec"  LOC = "E19"  ;
-#NET "miso_codec"  LOC = "F21"  ;
-#NET "sclk_codec"  LOC = "E20"  ;
-
 #NET "RXSYNC"  LOC = "F22"  ;
+#NET "reset_codec"  LOC = "D22"  ;
 
 #NET "DB<11>"  LOC = "E22"  ;
 #NET "DB<10>"  LOC = "J19"  ;
@@ -248,13 +255,12 @@ NET "io_rx<15>"  LOC = "Y4"  ;
 #NET "fpga_cfg_init_b"  LOC = "W15"  ;
 
 ## Unnamed, need to figure out what they do
-#NET "unnamed_net37"  LOC = "B1"  ;
-#NET "unnamed_net36"  LOC = "B22"  ;
-#NET "unnamed_net35"  LOC = "D2"  ;
-#NET "unnamed_net34"  LOC = "A21"  ;
-#NET "unnamed_net45"  LOC = "F7"  ;
-#NET "unnamed_net44"  LOC = "V6"  ;
-#NET "unnamed_net43"  LOC = "AA3"  ;
-#NET "unnamed_net42"  LOC = "AB3"  ;
-
-#NET "GND"  LOC = "V19"  ;
+#NET "unnamed_net37"  LOC = "B1"  ;  # TMS
+#NET "unnamed_net36"  LOC = "B22"  ; # TDO
+#NET "unnamed_net35"  LOC = "D2"  ;  # TDI
+#NET "unnamed_net34"  LOC = "A21"  ; # TCK
+#NET "unnamed_net45"  LOC = "F7"  ;  # PUDC_B
+#NET "unnamed_net44"  LOC = "V6"  ;  # M2
+#NET "unnamed_net43"  LOC = "AA3"  ; # M1
+#NET "unnamed_net42"  LOC = "AB3"  ; # M0
+#NET "GND"  LOC = "V19"  ;  # Suspend, unused
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
index 329d61aa9..f1f491a97 100644
--- a/usrp2/top/u1e/u1e.v
+++ b/usrp2/top/u1e/u1e.v
@@ -11,6 +11,12 @@ module u1e
    input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
 
    inout db_sda, inout db_scl, // I2C
+
+   output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx,   // DB TX SPI
+   output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx,   // DB TX SPI
+   output sclk_codec, output sen_codec, output mosi_codec, input miso_codec,   // AD9862 main SPI
+   output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso,     // Clock gen SPI
+   
    output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147,  // Fifo controls
    inout [15:0] io_tx, inout [15:0] io_rx
    );
@@ -21,6 +27,15 @@ module u1e
    IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
    clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
 
+   // SPI pins
+   wire  mosi, sclk, miso;
+   assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0;
+   assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0;
+   assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0;
+   assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0;
+   assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) |
+		 (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso);
+   
    u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]),
 		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
 		     .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
@@ -28,6 +43,7 @@ module u1e
 		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
 		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
 		     .db_sda(db_sda), .db_scl(db_scl),
+		     .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso),
 		     .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145),
 		     .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147),
 		     .io_tx(io_tx), .io_rx(io_rx) );
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 2645225a0..c74d385ee 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -9,6 +9,8 @@ module u1e_core
    input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
    
    inout db_sda, inout db_scl,
+   output sclk, output [7:0] sen, output mosi, input miso,
+   
    output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun,
    inout [15:0] io_tx, inout [15:0] io_rx
    );
@@ -187,14 +189,11 @@ module u1e_core
    // /////////////////////////////////////////////////////////////////////////////////////
    // Slave 2, SPI
 
-   /*
    spi_top shared_spi
      (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
       .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
       .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int),
-      .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
-      .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
-    */
+      .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) );
    
    // /////////////////////////////////////////////////////////////////////////
    // Slave 3, I2C
@@ -216,7 +215,7 @@ module u1e_core
 
    // /////////////////////////////////////////////////////////////////////////
    // GPIOs -- Slave #4
-/*
+
    wire [31:0] 	atr_lines;
    wire [31:0] 	debug_gpio_0, debug_gpio_1;
    
@@ -226,7 +225,7 @@ module u1e_core
 		.dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack),
 		.atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
 		.gpio( {io_tx,io_rx} ) );
-*/
+
    // /////////////////////////////////////////////////////////////////////////
    // Settings Bus -- Slave #5
 
@@ -247,7 +246,6 @@ module u1e_core
    assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
 		    { EM_D } };
 
-   assign {io_tx,io_rx} = debug_gpmc;
    assign debug_gpio_0 = { debug_gpmc };
    assign debug_gpio_1 = { debug_txd, debug_rxd };