updated pins to match rev2, removed dip switch, etc. seems to compile ok.

3 files changed, 130 insertions, 137 deletions

diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf
index 659a9dce5..51968d24a 100644
--- a/usrp2/top/u1e/u1e.ucf
+++ b/usrp2/top/u1e/u1e.ucf
@@ -54,8 +54,10 @@ NET "overo_gpio22"  LOC = "A3"  ;  # MISC GPIO for debug
 NET "overo_gpio23"  LOC = "B3"  ;  # MISC GPIO for debug
 NET "overo_gpio64"  LOC = "A4"  ;  # MISC GPIO for debug
 NET "overo_gpio65"  LOC = "F8"  ;  # MISC GPIO for debug
-NET "overo_gpio127"  LOC = "C8"  ;  # MISC GPIO for debug, also used on the passthru image as the cgen_sen_b pin
-NET "overo_gpio128"  LOC = "G8"  ;  # MISC GPIO for debug
+
+NET "overo_gpio127"  LOC = "C8"  ;  # Changed name to gpio10
+NET "overo_gpio128"  LOC = "G8"  ;  # Changed name to gpio186
+
 NET "overo_gpio144"  LOC = "A5"  ;  # tx_have_space
 NET "overo_gpio145"  LOC = "C7"  ;  # tx_underrun
 NET "overo_gpio146"  LOC = "A6"  ;  # rx_have_data
@@ -69,146 +71,137 @@ NET "overo_gpio176"  LOC = "B4"  ;  # MISC GPIO for debug
 #NET "overo_rxd1"  LOC = "D6"  ;
 
 ## FTDI UART to USB converter
-NET "FPGA_TXD"  LOC = "U1"  ;
-NET "FPGA_RXD"  LOC = "T6"  ;
+NET "FPGA_TXD"  LOC = "G19"  ;
+NET "FPGA_RXD"  LOC = "F20"  ;
 
 #NET "SYSEN"  LOC = "C11"  ;
 
 ## I2C
-NET "db_scl"  LOC = "U4"  ;
-NET "db_sda"  LOC = "U5"  ;
+NET "db_scl"  LOC = "F19"  ;
+NET "db_sda"  LOC = "F18"  ;
 
 ## SPI
 ### DBoard SPI
-NET "db_sclk_rx"  LOC = "W3"  ;
-NET "db_miso_rx"  LOC = "W2"  ;
-NET "db_mosi_rx"  LOC = "V4"  ;
-NET "db_sen_rx"  LOC = "V3"  ;
-NET "db_sclk_tx"  LOC = "Y1"  ;
-NET "db_miso_tx"  LOC = "W1"  ;
-NET "db_mosi_tx"  LOC = "R3"  ;
-NET "db_sen_tx"  LOC = "T4"  ;
+NET "db_sclk_rx"  LOC = "D21"  ;
+NET "db_miso_rx"  LOC = "D22"  ;
+NET "db_mosi_rx"  LOC = "D20"  ;
+NET "db_sen_rx"  LOC = "E19"  ;
+NET "db_sclk_tx"  LOC = "F21"  ;
+NET "db_miso_tx"  LOC = "E20"  ;
+NET "db_mosi_tx"  LOC = "G17"  ;
+NET "db_sen_tx"  LOC = "G18"  ;
 
 ### AD9862 SPI and aux SPI Interfaces
-#NET "aux_sdi_codec"  LOC = "F19"  ;
-#NET "aux_sdo_codec"  LOC = "F18"  ;
-#NET "aux_sclk_codec"  LOC = "D21"  ;
-NET "sen_codec"  LOC = "D20"  ;
-NET "mosi_codec"  LOC = "E19"  ;
-NET "miso_codec"  LOC = "F21"  ;
-NET "sclk_codec"  LOC = "E20"  ;
+#NET "aux_sdi_codec"  LOC = "G3"  ;
+#NET "aux_sdo_codec"  LOC = "F3"  ;
+#NET "aux_sclk_codec"  LOC = "C1"  ;
+NET "sen_codec"  LOC = "F5"  ;
+NET "mosi_codec"  LOC = "F4"  ;
+NET "miso_codec"  LOC = "H4"  ;
+NET "sclk_codec"  LOC = "H3"  ;
 
 ### Clock Gen SPI
-NET "cgen_miso"  LOC = "U2"  ;
-NET "cgen_mosi"  LOC = "V1"  ;
-NET "cgen_sclk"  LOC = "R5"  ;
-NET "cgen_sen_b"  LOC = "T1"  ;
+NET "cgen_miso"  LOC = "F22"  ;
+NET "cgen_mosi"  LOC = "E22"  ;
+NET "cgen_sclk"  LOC = "J19"  ;
+NET "cgen_sen_b"  LOC = "H20"  ;
 
 ## Clock gen control
-NET "cgen_st_status"  LOC = "D4"  ;
-NET "cgen_st_ld"  LOC = "D1"  ;
-NET "cgen_st_refmon"  LOC = "E1"  ;
-NET "cgen_sync_b"  LOC = "M1"  ;
-NET "cgen_ref_sel"  LOC = "J1"  ;
+NET "cgen_st_status"  LOC = "P20"  ;
+NET "cgen_st_ld"  LOC = "R17"  ;
+NET "cgen_st_refmon"  LOC = "P17"  ;
+NET "cgen_sync_b"  LOC = "U18"  ;
+NET "cgen_ref_sel"  LOC = "U19"  ;
 
 ## Debug pins
-NET "debug_led<2>"  LOC = "T5"  ;
-NET "debug_led<1>"  LOC = "R2"  ;
-NET "debug_led<0>"  LOC = "R1"  ;
-NET "debug<0>"  LOC = "P6"  ;
-NET "debug<1>"  LOC = "R6"  ;
-NET "debug<2>"  LOC = "P1"  ;
-NET "debug<3>"  LOC = "P2"  ;
-NET "debug<4>"  LOC = "N6"  ;
-NET "debug<5>"  LOC = "N5"  ;
-NET "debug<6>"  LOC = "N1"  ;
-NET "debug<7>"  LOC = "K2"  ;
-NET "debug<8>"  LOC = "K3"  ;
-NET "debug<9>"  LOC = "K6"  ;
-NET "debug<10>"  LOC = "L5"  ;
-NET "debug<11>"  LOC = "H2"  ;
-NET "debug<12>"  LOC = "K4"  ;
-NET "debug<13>"  LOC = "K5"  ;
-NET "debug<14>"  LOC = "G1"  ;
-NET "debug<15>"  LOC = "H1"  ;
-NET "debug<16>"  LOC = "H5"  ;
-NET "debug<17>"  LOC = "H6"  ;
-NET "debug<18>"  LOC = "E3"  ;
-NET "debug<19>"  LOC = "E4"  ;
-NET "debug<20>"  LOC = "G5"  ;
-NET "debug<21>"  LOC = "G6"  ;
-NET "debug<22>"  LOC = "F2"  ;
-NET "debug<23>"  LOC = "F1"  ;
-NET "debug<24>"  LOC = "H3"  ;
-NET "debug<25>"  LOC = "H4"  ;
-NET "debug<26>"  LOC = "F4"  ;
-NET "debug<27>"  LOC = "F5"  ;
-NET "debug<28>"  LOC = "C2"  ;
-NET "debug<29>"  LOC = "C1"  ;
-NET "debug<30>"  LOC = "F3"  ;
-NET "debug<31>"  LOC = "G3"  ;
-NET "debug_clk<0>"  LOC = "L6"  ;
-NET "debug_clk<1>"  LOC = "M5"  ;
+NET "debug_led<3>"  LOC = "Y15"  ;
+NET "debug_led<2>"  LOC = "K16"  ;
+NET "debug_led<1>"  LOC = "J17"  ;
+NET "debug_led<0>"  LOC = "H22"  ;
+NET "debug<0>"  LOC = "G22"  ;
+NET "debug<1>"  LOC = "H17"  ;
+NET "debug<2>"  LOC = "H18"  ;
+NET "debug<3>"  LOC = "K20"  ;
+NET "debug<4>"  LOC = "J20"  ;
+NET "debug<5>"  LOC = "K19"  ;
+NET "debug<6>"  LOC = "K18"  ;
+NET "debug<7>"  LOC = "L22"  ;
+NET "debug<8>"  LOC = "K22"  ;
+NET "debug<9>"  LOC = "N22"  ;
+NET "debug<10>"  LOC = "M22"  ;
+NET "debug<11>"  LOC = "N20"  ;
+NET "debug<12>"  LOC = "N19"  ;
+NET "debug<13>"  LOC = "R22"  ;
+NET "debug<14>"  LOC = "P22"  ;
+NET "debug<15>"  LOC = "N17"  ;
+NET "debug<16>"  LOC = "P16"  ;
+NET "debug<17>"  LOC = "U22"  ;
+NET "debug<18>"  LOC = "P19"  ;
+NET "debug<19>"  LOC = "R18"  ;
+NET "debug<20>"  LOC = "U20"  ;
+NET "debug<21>"  LOC = "T20"  ;
+NET "debug<22>"  LOC = "R19"  ;
+NET "debug<23>"  LOC = "R20"  ;
+NET "debug<24>"  LOC = "W22"  ;
+NET "debug<25>"  LOC = "Y22"  ;
+NET "debug<26>"  LOC = "T18"  ;
+NET "debug<27>"  LOC = "T17"  ;
+NET "debug<28>"  LOC = "W19"  ;
+NET "debug<29>"  LOC = "V20"  ;
+NET "debug<30>"  LOC = "Y21"  ;
+NET "debug<31>"  LOC = "AA22"  ;
+NET "debug_clk<0>"  LOC = "N18"  ;
+NET "debug_clk<1>"  LOC = "M17"  ;
 
-NET "debug_pb<2>"  LOC = "Y2"  ;
-NET "debug_pb<1>"  LOC = "AA1"  ;
-NET "debug_pb<0>"  LOC = "N3"  ;
+NET "debug_pb"  LOC = "C22"  ;
 
-NET "dip_sw<7>"  LOC = "T3"  ;
-NET "dip_sw<6>"  LOC = "U3"  ;
-NET "dip_sw<5>"  LOC = "M3"  ;
-NET "dip_sw<4>"  LOC = "N4"  ;
-NET "dip_sw<3>"  LOC = "J3"  ;
-NET "dip_sw<2>"  LOC = "J4"  ;
-NET "dip_sw<1>"  LOC = "J6"  ;
-NET "dip_sw<0>"  LOC = "J7"  ;
+#NET "reset_codec"  LOC = "C2"  ;
 
-#NET "reset_codec"  LOC = "D22"  ;
+NET "RXSYNC"  LOC = "F2"  ;
+NET "DB<11>"  LOC = "G6"  ;
+NET "DB<10>"  LOC = "G5"  ;
+NET "DB<9>"  LOC = "E4"  ;
+NET "DB<8>"  LOC = "E3"  ;
+NET "DB<7>"  LOC = "H6"  ;
+NET "DB<6>"  LOC = "H5"  ;
+NET "DB<5>"  LOC = "H1"  ;
+NET "DB<4>"  LOC = "G1"  ;
+NET "DB<3>"  LOC = "K5"  ;
+NET "DB<2>"  LOC = "K4"  ;
+NET "DB<1>"  LOC = "H2"  ;
+NET "DB<0>"  LOC = "L5"  ;
 
-NET "RXSYNC"  LOC = "F22"  ;
-NET "DB<11>"  LOC = "E22"  ;
-NET "DB<10>"  LOC = "J19"  ;
-NET "DB<9>"  LOC = "H20"  ;
-NET "DB<8>"  LOC = "G19"  ;
-NET "DB<7>"  LOC = "F20"  ;
-NET "DB<6>"  LOC = "K16"  ;
-NET "DB<5>"  LOC = "J17"  ;
-NET "DB<4>"  LOC = "H22"  ;
-NET "DB<3>"  LOC = "G22"  ;
-NET "DB<2>"  LOC = "H17"  ;
-NET "DB<1>"  LOC = "H18"  ;
-NET "DB<0>"  LOC = "K20"  ;
-NET "DA<11>"  LOC = "J20"  ;
-NET "DA<10>"  LOC = "K19"  ;
-NET "DA<9>"  LOC = "K18"  ;
-NET "DA<8>"  LOC = "L22"  ;
-NET "DA<7>"  LOC = "K22"  ;
-NET "DA<6>"  LOC = "N22"  ;
-NET "DA<5>"  LOC = "M22"  ;
-NET "DA<4>"  LOC = "N20"  ;
-NET "DA<3>"  LOC = "N19"  ;
-NET "DA<2>"  LOC = "R22"  ;
-NET "DA<1>"  LOC = "P22"  ;
-NET "DA<0>"  LOC = "N17"  ;
+NET "DA<11>"  LOC = "K6"  ;
+NET "DA<10>"  LOC = "K3"  ;
+NET "DA<9>"  LOC = "K2"  ;
+NET "DA<8>"  LOC = "N1"  ;
+NET "DA<7>"  LOC = "N5"  ;
+NET "DA<6>"  LOC = "N6"  ;
+NET "DA<5>"  LOC = "P2"  ;
+NET "DA<4>"  LOC = "P1"  ;
+NET "DA<3>"  LOC = "R6"  ;
+NET "DA<2>"  LOC = "P6"  ;
+NET "DA<1>"  LOC = "R1"  ;
+NET "DA<0>"  LOC = "R2"  ;
 
-NET "TX<13>"  LOC = "P19"  ;
-NET "TX<12>"  LOC = "R18"  ;
-NET "TX<11>"  LOC = "U20"  ;
-NET "TX<10>"  LOC = "T20"  ;
-NET "TX<9>"  LOC = "R19"  ;
-NET "TX<8>"  LOC = "R20"  ;
-NET "TX<7>"  LOC = "W22"  ;
-NET "TX<6>"  LOC = "Y22"  ;
-NET "TX<5>"  LOC = "T18"  ;
-NET "TX<4>"  LOC = "T17"  ;
-NET "TX<3>"  LOC = "W19"  ;
-NET "TX<2>"  LOC = "V20"  ;
-NET "TX<1>"  LOC = "Y21"  ;
-NET "TX<0>"  LOC = "AA22"  ;
-NET "TXSYNC"  LOC = "U18"  ;
-NET "TXBLANK"  LOC = "U19"  ;
+NET "TX<13>"  LOC = "T6"  ;
+NET "TX<12>"  LOC = "U1"  ;
+NET "TX<11>"  LOC = "T1"  ;
+NET "TX<10>"  LOC = "R5"  ;
+NET "TX<9>"  LOC = "V1"  ;
+NET "TX<8>"  LOC = "U2"  ;
+NET "TX<7>"  LOC = "T4"  ;
+NET "TX<6>"  LOC = "R3"  ;
+NET "TX<5>"  LOC = "W1"  ;
+NET "TX<4>"  LOC = "Y1"  ;
+NET "TX<3>"  LOC = "V3"  ;
+NET "TX<2>"  LOC = "V4"  ;
+NET "TX<1>"  LOC = "W2"  ;
+NET "TX<0>"  LOC = "W3"  ;
+NET "TXSYNC"  LOC = "U5"  ;
+NET "TXBLANK"  LOC = "U4"  ;
 
-NET "PPS_IN"  LOC = "M17"  ;
+NET "PPS_IN"  LOC = "M5"  ;
 
 NET "io_tx<0>"  LOC = "AB20"  ;
 NET "io_tx<1>"  LOC = "Y17"  ;
@@ -255,12 +248,12 @@ NET "io_rx<15>"  LOC = "Y4"  ;
 #NET "fpga_cfg_init_b"  LOC = "W15"  ;
 
 ## Unused
-#NET "unnamed_net37"  LOC = "B1"  ;  # TMS
-#NET "unnamed_net36"  LOC = "B22"  ; # TDO
-#NET "unnamed_net35"  LOC = "D2"  ;  # TDI
-#NET "unnamed_net34"  LOC = "A21"  ; # TCK
-#NET "unnamed_net45"  LOC = "F7"  ;  # PUDC_B
-#NET "unnamed_net44"  LOC = "V6"  ;  # M2
-#NET "unnamed_net43"  LOC = "AA3"  ; # M1
-#NET "unnamed_net42"  LOC = "AB3"  ; # M0
+#NET "unnamed_net53"  LOC = "B1"  ;  # TMS
+#NET "unnamed_net52"  LOC = "B22"  ; # TDO
+#NET "unnamed_net51"  LOC = "D2"  ;  # TDI
+#NET "unnamed_net50"  LOC = "A21"  ; # TCK
+#NET "unnamed_net59"  LOC = "F7"  ;  # PUDC_B
+#NET "unnamed_net58"  LOC = "V6"  ;  # M2
+#NET "unnamed_net57"  LOC = "AA3"  ; # M1
+#NET "unnamed_net56"  LOC = "AB3"  ; # M0
 #NET "GND"  LOC = "V19"  ;  # Suspend, unused
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
index 9536b5ced..7ddbfd537 100644
--- a/usrp2/top/u1e/u1e.v
+++ b/usrp2/top/u1e/u1e.v
@@ -5,8 +5,8 @@
 
 module u1e
   (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
-   output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
-   input [2:0] debug_pb, input [7:0] dip_sw, output FPGA_TXD, input FPGA_RXD,
+   output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+   input debug_pb, output FPGA_TXD, input FPGA_RXD,
 
    // GPMC
    input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
@@ -137,9 +137,9 @@ module u1e
    
    // /////////////////////////////////////////////////////////////////////////
    // Main U1E Core
-   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]),
+   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb),
 		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
-		     .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
+		     .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
 		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
 		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
 		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 5c4b6de6c..42333a722 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -6,8 +6,8 @@
 
 module u1e_core
   (input clk_fpga, input rst_fpga,
-   output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
-   input [2:0] debug_pb, input [7:0] dip_sw, output debug_txd, input debug_rxd,
+   output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+   output debug_txd, input debug_rxd,
    
    // GPMC
    input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
@@ -343,11 +343,11 @@ module u1e_core
    assign rx_enable = xfer_rate[14];
    assign rate = xfer_rate[7:0];
    
-   assign { debug_led[2],debug_led[0],debug_led[1] } = {run_rx,run_tx,reg_leds[0]};  // LEDs are arranged funny on board
+   assign { debug_led[3:0] } = {run_rx,run_tx,reg_leds[1:0]};
    assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
    
    assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : 
-			(s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} :
+			(s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } :
 			(s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
 			(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
 			(s0_adr[6:0] == REG_TEST) ? reg_test :