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author | Matt Ettus <matt@ettus.com> | 2010-02-22 12:30:22 -0800 |
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committer | Matt Ettus <matt@ettus.com> | 2010-02-22 12:30:22 -0800 |
commit | 2e4d962021334109b268c9080e5a5903b99be217 (patch) | |
tree | e9196d30450a0c2dc5fa0485a9c597c26f160441 /usrp2/top/u1e/u1e.v | |
parent | bc3c1fb34afba5fb4358f1b7eaaf3832360cc375 (diff) | |
download | uhd-2e4d962021334109b268c9080e5a5903b99be217.tar.gz uhd-2e4d962021334109b268c9080e5a5903b99be217.tar.bz2 uhd-2e4d962021334109b268c9080e5a5903b99be217.zip |
GPIOs now on the wishbone interface
Diffstat (limited to 'usrp2/top/u1e/u1e.v')
-rw-r--r-- | usrp2/top/u1e/u1e.v | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 326476b21..667372434 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -11,7 +11,8 @@ module u1e input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, // I2C - output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147 // Fifo controls + output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls + inout [15:0] io_tx, inout [15:0] io_rx ); // FPGA-specific pins connections @@ -27,6 +28,7 @@ module u1e .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), - .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147) ); + .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), + .io_tx(io_tx), .io_rx(io_rx) ); endmodule // u1e |