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| author | Matt Ettus <matt@ettus.com> | 2010-02-25 16:50:09 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-02-25 16:50:09 -0800 |
| commit | 030f6a21539207c058b982ffade384ec7a937ec2 (patch) | |
| tree | 8432bb4f2536604762a81b1c6847687bb77c2819 /usrp2/top/u1e/u1e.v | |
| parent | 0d9c46ae002cad7c144432e86987a81eb33157fc (diff) | |
| download | uhd-030f6a21539207c058b982ffade384ec7a937ec2.tar.gz uhd-030f6a21539207c058b982ffade384ec7a937ec2.tar.bz2 uhd-030f6a21539207c058b982ffade384ec7a937ec2.zip | |
First cut at passing data buffers around on GPMC bus
Diffstat (limited to 'usrp2/top/u1e/u1e.v')
| -rw-r--r-- | usrp2/top/u1e/u1e.v | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 667372434..066d02ca4 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -21,7 +21,8 @@ module u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(debug_pb[2]), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .debug_pb(debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), |